• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.84-92
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• 2010

색채선별기는 양질의 곡물 유통을 위해 불량곡물, 이물질을 선별하는 시스템이다. 기존의 색채 선별기는 PC기반 제어시스템으로서 비교적 고가이고 부피가 크며 현장 환경에서 기계적 충격이나 먼지등에 취약하다는 문제점을 가지고 있다. 본 논문에서는 이러한 문제점을 개선하기 위해 운영체제가 탑재된 임베디드 제어기 기반의 색채선별기를 제안한다. 색채선별기는 기본적으로 곡물의 유입량 및 속도를 조절해 주는 피터부, 곡물의 영상을 받아 이미지를 처리해 주는 카메라부, 카메라부에서 받은 정보를 이용해 양품과 불량품을 분리해 주는 이젝터부로 구성된다. 본 논문에서는 개발된 지능형 색채선별기용 ARM 프로세서 기반 임베디드 제어기의 하드웨어 구성, 피더부, 카메라부, 이젝터부 간의 통신프로토콜을 이용한 총괄관리 제어와 그래픽 사용자 인터페이스(GUI)를 소개한다.

• Journal of IKEEE
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• v.16 no.4
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• pp.382-388
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• 2012

An H.264/AVC fast motion estimation methodology is presented in this paper. Advanced SIMD based NEON which is one of the parallel processing methods is supported under the ARM Cortex-A9 dual-core platform. NEON is applied to a full search technique with one of the various motion estimation methods and SAD operation count of each macroblock is reduced to 1/4. Pixel values of the corresponding macroblock are assigned to eight 16-bit NEON registers and Intrinsic function in NEON architecture carried out 128 bits arithmetic operations at the same time. In this way, the exact motion vector with the minimum SAD value among the calculated SAD values can be designated. Experimental results show that performance gets improved 30% above average in accordance with the size of image and macroblock.

• Journal of IKEEE
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• v.21 no.1
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• pp.92-95
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• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.99-105
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• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.4
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• pp.233-239
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• 2015

This paper describes a method that is integrated trace for real-time virtualization environment. This method has solved the problem that the performance trace may not be able to analyze integrated method between heterogeneous operating systems which is consists of real-time operating systems and general-purpose operating system. In order to solve this problem, we have attempted to reuse the performance analysis function in general-purpose operating system, thereby real-time operating systems can be analyzed along with general-operating system. Furthermore, we have implemented a prototype based on ARM Cortex-A15 dual-core processor. By using this integrated trace method, real-time system developers can be improved productivity and reliability of results on real-time virtualization environment.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2009.04a
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• pp.561-566
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• 2009

The outrigger system with a core is widely used for lateral load resisting system of tall building. Recently, structural systems in tall building are adopted to eccentric core and offset outrigger or one-armed outrigger system by trends in planning buildings of irregular type. Therefore, the performance of outrigger system with eccentric core in tall building is evaluated by 50-stories examples which are analyzed for variables such as layout of core and outrigger, arm length of outrigger and depth of outrigger and belt wall.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• Annual Conference on Human and Language Technology
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• 2015.10a
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• pp.231-233
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• 2015

본 논문에서는 심층 신경망 기반의 내장형 음성 인식 시스템에서 음성 인식 속도를 개선하기 위한 최적화 방법에 대해 논한다. 심층 신경망 기반의 음성 인식은 기존의 Gaussian Mixture Model (GMM) 기반에 비해 좋은 인식 성능을 보이지만 높은 연산량으로 인해 리소스가 제약된 내장형 단말기에 적용하기에는 어려움이 따른다. 따라서, 본 연구에서는 심층 신경망의 계산량 문제를 해결하고자 ARM 코어에 내장된 병렬 명령어를 사용한 최적화 기법과 특이값 분해를 통해 심층 신경망 매트릭스 연산량 감소 방안에 대해 제안한다.