• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.1-12
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• 1998

We have implemented receiver for a 3 Dimensional Phased-Array Radar detecting the azimuth angle, the altitude, the range of a target on real time. This system consists of high frequency module, which protects receiver and controls sensitivity, intermediate frequency module, monopulse detector, IQ phase detector, AGC controller. A two-channel receiver with same function is implemented for increasing accuracy of target altitude data by amplitude comparison monopulse method. The TSS sensitivity of the receiver is -98dBm. The bandwidth of the receiver is 500 MHz. We can control the system gain manually by 100 dB when be AGC off. The gain and phase unbalance of two channels is 5 dB and 30 degree, respectively. The image rejection rate of the IQ detector is 30 dB. We used duroid substrate and package- type device.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.1
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• pp.94-102
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• 2018

In this paper, the wideband mono-pulse radar using AGC and limiter is designed. The output response characteristics of the mono-pulse radar using AGC and limiter are analyzed, respectively. In addition, the output response for jamming input signals is analyzed. The range tracking loop in the mono-pulse radar has robust output response to the noise jamming input signal. Although the output settling response of the AGC-based mono-pulse radar is larger than that of the limiter-based mono-pulse radar, the AGC-based mono-pulse radar has robustness to the noise jamming input signal due to feedback loop.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.45-49
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• 1985

This paper presents a simple method for drastic reduction of computational requirement for realization of the quasi.noise alone reference (QNAR) estimation of noise power. (1 ) The new estimator docs not bring forth performance degradation, as shown by extensive computer simulations, and is amenable to hardware implementation for certain real-time signal processing problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.128-137
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• 2012

When a CCD camera acquires images in the low light level environment, not only the image signals but also noise components are amplified by the AGC (auto gain control) circuit. Since the noise level in the images acquired in the dark is very high, it is difficult to remove noise with existing denoising algorithms that are targeting the images taken in the normal light condition. In this paper, we proposed an adaptive denoising algorithm that can efficiently remove significant noises caused by the low light level. First, the window including a target pixel is transformed to the frequency domain. Then the algorithm compares the characteristics of equally divided four frequency bands. Finally the noises are adaptively removed according to the frequency characteristics. The proposed algorithm successfully improves the quality of low light level images than the existing algorithms do.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.479-486
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• 2008

In this paper, an efficient training symbol design with m-sequence is proposed for the MIMO-OFDM based next generation wireless transmission system which supports gigabits per second data rate. In the traditional blute force method, the preamble design is based on the case by case comparison with the system requirements. This paper discusses a training symbol design methodology for the MIMO-OFDM system based on the m-sequence which has been widely used in the spread spectrum communication areas due to its good correlation characteristics. Also the step-by-step design and performance verification method within the limited search space is discussed. The proposed method targets the design of the training symbol which satisfies system requirements for the packet based MIMO-OFDM wireless communication system including automatic gain control(AGC), timing synchronization, frequency and sampling offset estimation, and MIMO channel estimation.