• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.3
• /
• pp.160-165
• /
• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.6
• /
• pp.380-385
• /
• 2016

Thermal characteristics of 20 W LED module on light thermal conductive plastic (TCP) heat sink were investigated in comparison with that on aluminum die casting alloy (ADC-12). Thermal simulations of the heat sinks were conducted by using flow simulation of SolidWorks with the following input parameters: density is 1.70 and $2.82kg/m^2$, thermal conductivity is 20 and $92W/(m{\cdot}K)$ for TCP and ADC-12, respectively. The simulated and measured temperatures of the LED modules on TCP heat sink were consistent with its measured temperature, which was $3^{\circ}C$ higher that on ADC-12. The fabricated LED module on TCP heat sink with a weight of 120.5 g was 30% lighter in weight than that of the ADC-12 reference with 171.0 g.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.22-28
• /
• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.69-76
• /
• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of Sensor Science and Technology
• /
• v.27 no.1
• /
• pp.31-35
• /
• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.12
• /
• pp.22-28
• /
• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.31 no.1
• /
• pp.24-31
• /
• 2021

We report structural, mechanical, and thermal properties of diecast ADC12 aluminum alloys characterized using synchrotron X-ray diffraction (XRD), scanning electron microscopy, energy dispersive X-ray (EDX) analysis, thermal conductivity (λ), Vickers hardness (Hv), and stress-strain measurements. We also studied the effect of post-annealing performed in a vacuum atmosphere on the mechanical properties of diecast ADC12 alloys. EDX and XRD results revealed that Al2Cu and AlCu3 grains are formed, well dispersed in Al base and highly crystalline. Ultimate tensile strength (UTS) of 307.9 ± 9.1 MPa and elongation of 2.98 ± 0.62 % were estimated. λ was 129.3 ± 0.27 W/m·K and Hv was approximately 130. Both values were significantly higher than the reported values. At annealing temperatures ranging from 25 to 200℃, UTS and Hv values remained constant, while as the annealing temperature increased to 500℃, these values gradually decreased. This is because stabilization of the microstructure improves toughness and ductility.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.189-197
• /
• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• Journal of Korea Foundry Society
• /
• v.36 no.3
• /
• pp.88-94
• /
• 2016

We investigated the effect of heat treatment on an ADC12 alloy produced using diecasting. The heat treatment used in this study was a typical T6 process: a solid solution treatment followed by an artificial aging treatment. As-cast specimens were solid-solution-treated at $500^{\circ}C$ and $530^{\circ}C$ for 1-16 hr, and aged at $160^{\circ}C$ and $180^{\circ}C$ for 1-8 hr. Microstructural changes in the alloy during the heat treatment were observed. Changes in mechanical properties of the alloy were measured using a micro-Vickers hardness tester. Finally, we determined the optimal heat treatment conditions for the diecast ADC12 alloy.

• Journal of the Korean institute of surface engineering
• /
• v.49 no.2
• /
• pp.130-134
• /
• 2016

The anodization of ADC12 aluminum alloy was investigated in the metal anionic acid media. Anodic oxide films containing foreign elements were formed on ADC12 Al alloy by anodization in the anion complex solution. Furthermore, the rough surface and cracks were considerably smoothened by the deposit of metal anions. When the size of metal anion was small, relatively large amount of metal anions was loaded in anodic films. Existence of $MoO_3$, $TiO_2$ and MgO was confirmed by XPS. According to the results of Tafel analysis, Mo oxide represented the most noble anti-corrosion potential due to $MoS_2$ formation. Corrosion current densities were generally higher than that of pristine anodic oxide without anion complexes.