• The Magazine of the IEIE
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• v.38 no.1
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• pp.56-67
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• 2011

As a result of quickly growing data, a digital transmission system is required to deal with the challenge of acquiring signals at a very high sampling rate, Fortunately, the CS (Compressed Sensing or Compressive Sensing) theory, a new concept based on theoretical results of signal reconstruction, can be employed to exploit the sparsity of the received signals. Then, they can be adequately reconstructed from a set of their random projections, leading to dramatic reduction in the sampling rate and in the use of ADC (Analog-to-Digital Converter) resources. The goal of this article is provide an overview of the basic CS theory and to survey some important compressed sensing applications in wireless communications.

• International journal of advanced smart convergence
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• v.8 no.4
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• pp.154-160
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• 2019

In this paper, we propose the miniaturization size of wearable Range of Motion(ROM) and a system that can be connected with smart devices in real-time to measure the joint movement range dynamically. Currently, the ROM of the joint is directly measured by a person using a goniometer. Conventional methods are different depending on the measurement method and location of the measurement person, which makes it difficult to measure consistently and may cause errors. Also, it is impossible to measure the ROM of joints in real-life situations. Therefore, the wearable sensor is attached to the joint to be measured to develop a miniaturize size ROM device that can measure the range of motion of the joint in real-time. The sensor measured the resistance value changed according to the movement of the joint using a load cell. Also, the sensed analog values were converted to digital values using an Analog to Digital Converter(ADC). The converted amount can be transmitted wireless to the smart device through the wearable sensor node. As a result, the developed device can be measured more consistently than the measurement using the goniometer, communication with IoT-based smart devices, and wearable enables dynamic observation. The developed wearable sensor node will be able to monitor the dynamic state of rehabilitation patients in real-time and improve the rapid change of treatment method and customized treatment.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.462-468
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• 2012

In this paper, an adaptive digital automatic gain control(AGC) algorithm with two stages is proposed. AGC technique is crucial for mobile communication equipment because path loss in wireless channel and gain fluctuation in receiver front-end continuously change the received signal strength. Furthermore, adaptive criteria should be applied to the design of AGC algorithm in order to support many waveforms with one SDR communication device. With these reasons, a two-stage structure is proposed to satisfy both flexibility and adaptiveness. Compared with conventional method, it also requires shorter convergence time. Numerical results show that the gain value of variable gain amplifier(VGA) is converged within proper time and proposed scheme controls the input level of analog to digital converter(ADC) to be stable during long range of time.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.105-110
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• 2009

The techniques of intelligent interference cancellation are used for achieving the improvement of deterioration, which is arisen to the interoperable terminal(GSM and DVB-H). In this paper, we propose a novel system that improve the DVB-H received performance by using the method of an adaptive interference canceller for GSM900 and DVB-H terminal. The interference for the collocated GSM900 and DVB-H receiver is cancelled by using the adaptive canceller with the low-noise ADC(Analog to Digital Converter) in the RF stage.