• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.76-79
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• 2010

본 논문에서는 고 효율 및 고 출력 특성을 가지는 질화갈륨(GaN) 소자를 이용하여 WiMAX 및 LTE System에 사용될 수 있는 DPD용 Pallet Amplifier를 제작하였다. 제작된 Pallet Amplifier는 Pre-drive로써 저 전류의 MMIC를 채택하고, Drive 단과 Main 단에 15W 급과 30W 급의 질화갈륨 소자를 사용 하였으며, 추가적인 효율 개선을 위해 PCB상에 Doherty Structure를 적용함으로써 보다 높은 효율을 구현하였다. 제작된 Pallet Amplifier는 음 전원 Bias 제어 회로, 온도에 따른 Gain 보상회로, Sequence 회로 및 Main 전원 Drop에 따른 보호 회로를 구현하였다. WiMAX Signal을 이용한 Modulation Power 10Watt Test에서 약 36.8~38.3%의 Pallet 효율과 DPD Solution인 TI GC5325SEK DPD Board 사용 시 ACLR은 약 46dBc 이상을 가지는 것으로 측정되었다. 본 논문에서 제작된 Pallet Amplifier는 Upper Band와 Lower Band로 나누어 제작되었던 기존 Pallet Amplifier와 달리 하나의 Pallet Amplifier로 2496~2690MHz에서 모두 사용하면서 종전에 사용되고 있는 Pallet Amplifier에 비해 Size가 최소 10% 이상 축소되어 효율 및 크기 면에서 종전 Pallet Amplifier보다 큰 이점을 갖는다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.974-978
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• 2003

The down-converter of the WCDMA Digital Optic Repeater is developed. Based on the system specifications, the structure of the down-converter is accomplished and its block diagram is drawn. The down-converter is implemented according to these block diagrams. Subsequently a low pass filter, an automatic level controlled attenuator, a frequency synthesizer and other components for the down-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the down-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.147-153
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• 2007

This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.

• Journal of electromagnetic engineering and science
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• v.15 no.1
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• pp.53-58
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• 2015

For the testing of nonlinear power amplifiers, this paper suggests an approach to design optimized multisine signals that could be substituted for the original modulated signal. In the design of multisines, complex coefficients should be determined to mimic the target signal as much as possible, but very few methods have been adopted as general solutions to the coefficients. Furthermore, no solid method for the phase of coefficients has been proven to show the best resemblance to the original. Therefore, in order to determine the phase of multisine coefficients, a time-domain nonlinear optimization method is suggested. A frequency-domain-method based on the spectral response of the target signal is also suggested for the magnitude of the coefficients. For the verification, multisine signals are designed to emulate the LTE downlink signal of 10 MHz bandwidth and are used to test a nonlinear amplifier at 1.9 GHz. The suggested phase-optimized multisine had a lower normalized error by 0.163 dB when N = 100, and the measurement results showed that the suggested multisine achieved more accurate adjacent-channel leakage ratio (ACLR) estimation by as much as 12 dB compared to that of the conventional iterative method.

• The Journal of Korean Physical Therapy
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• v.31 no.4
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• pp.161-168
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• 2019

Most athletes with anterior cruciate ligament (ACL) ruptures undergo a surgical ACL reconstruction (ACLR) and rehabilitation. On the other hand, controversy still exists because neither a reconstruction nor rehabilitation have been proven to be superior in the management of ACL injury. This study reviewed the success rates of interventions to provide recommendations for the optimal management after an ACL injury. One of the most important considerations after an ACL injury is the timing and type of intervention. At the early stages, which involve the loss of volume and strength of quadriceps femoral muscle, weight bearing (closed kinetic chain) exercises with pain management followed by high velocity resistance exercises in an open kinetic chain environment are recommended to improve the quadriceps function. After that, it is important to apply intensive isokinetic exercise with a lower extension rate. In this case, it is important to apply overload to the muscles and to simultaneously lead the co-contraction of the hamstrings. Standards are essential because the timing and type of interventions are crucial to prevent re-injury and complications, such as osteoarthritis, as well as to confirm the successful outcome of the treatment. Different interventions recommended for ACL damage have yet to reach consensus. Further studies will be needed to observe the effects of the intervention through multidisciplinary approaches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.339-345
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• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

• Journal of Advanced Navigation Technology
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• v.27 no.2
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• pp.197-202
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• 2023

This paper presents the design method and electrical characteristics of a high-efficiency power amplifier for a 50 Watts class repeater applied to a 5G system and used in in-building, subway, and tunnel. GaN was used for the termination transistor of the power amplifier designed here, and intermodulation signals were removed using DPD to satisfy linearity. In addition, in order to handle various requirements such as amplifier gain control and alarm processing required in the 5G system, the microprocessor is designed to exist inside the power amplifier. The amplifier manufactured to confirm the electrical performance of the power amplifier satisfying these conditions satisfied 46.5 dBm and the overall efficiency of the amplifier was 37%, and it was confirmed that it satisfied various alarm conditions and electrical characteristics required by telecommunication companies.

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.26-36
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• 2014

The needs of active phased arrays antenna system is getting more increased for IMT-Advanced system efficiency. The active phased array structure consists of lots of small transceivers and radiation elements to increase system efficiency. The minimized module of high efficiency transceiver is key for system implementation. The power amplifier of transmitter decides efficiency of base-station. In this paper, we design and implement minimized module of high efficiency transceiver for IMT-Advanced active phased array system. The temperature compensation circuit of transceiver reduces gain error and the analog pre-distorter of linearizer reduces implemented size. For minimal size and high efficiency, the implented power amplifier consist of GaN MMIC Doherty structure. The size of implemented module is $40mm{\times}90mm{\times}50mm$ and output power is 47.65 dBm at LTE band 7. The efficiency of power amplifier is 40.7% efficiency and ACLR compensation of linearizer is above 12dB at operating power level, 37dBm. The noise figure of transceiver is under 1.28 dB and amplitude error and phase error on 6 bit control is 0.38 dB and 2.77 degree respectively.