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Design and Implementation of Voltage-controlled Oscillator for 380 MHz TRS Handset (380 MHz대 TRS 단말기용 전압제어 발진기 설계 및 제작)

  • 홍성용
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.9 no.2
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    • pp.219-225
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    • 1998
  • A voltage controlled oscillator for the local oscillator in 380 MHz TRS handset is designed and fabricated. To improve the phase noise characteristics, the NEC's 2SC4226 transistor with NF=1.2 at 1 GHz and Toshiba's 1SV229 varactor diode with Q=70 are used. And an inductor of VCO is realized by microstrip line. At the bias condition of 5 V and 10 mA, the output power and phase noise in the operating frequency range of 357∼387 MHz are above 3.7 dBm and 111 dBc/Hz at 12.5KHz offset from the carrier, respectively. And FM sensitivity deviation are within ±0.4 KHz. This VCO is well suited for TRS handset.

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Design of a Low Phase Noise Voltage Tuned Planar Composite Resonator Oscillator Using SIW Structure (SIW 구조를 이용한 저 위상잡음 전압 제어 평판형 복합공진기 발진기 설계)

  • Lee, Dong-Hyun;Son, Beom-Ik;Yeom, Kyung-Whan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.5
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    • pp.515-525
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    • 2014
  • In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

A CMOS Fractional-N Frequency Synthesizer for DTV Tuners (DTV 튜너를 위한 CMOS Fractional-N 주파수합성기)

  • Ko, Seung-O;Seo, Hee-Teak;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.14 no.1
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    • pp.65-74
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    • 2010
  • The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

Design of Broadband 12 ㎓ Active Frequency Doubler using PHEMT (PHEMT를 이용한 광대역 12 ㎓ 능동 주파수 체배기 설계)

  • 전종환;강성민;최재홍;구경헌
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.6
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    • pp.560-566
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    • 2004
  • In this paper, active frequency doubler with broadband characteristics from 6 ㎓ to 12 ㎓ was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed series RC circuit between bias line and input matching network far the improvement of stability. With 0 ㏈m input power, second harmonic of 1.7 ㏈m at 12 ㎓ -27.5 ㏈c suppression of 6 ㎓ fundamental, -18 ㏈c suppression of 18 ㎓ 3rd harmonic, and the 3 ㏈ output bandwidth of 1,8 ㎓ have been measured.

Design of a New Harmonic Noise Frequency Filtering Down-Converter in InGaP/GaAs HBT Process

  • Wang, Cong;Yoon, Jae-Ho;Kim, Nam-Young
    • Journal of electromagnetic engineering and science
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    • v.9 no.2
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    • pp.98-104
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    • 2009
  • An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

Design of Reflector Type Frequency Doubler for Undesired Harmonic Suppression Using Harmonic Load Pull Simulation Technique

  • Jang, Jae-Woong;Kim, Yong-Hoon
    • Journal of electromagnetic engineering and science
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    • v.7 no.4
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    • pp.175-182
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    • 2007
  • In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.

Effect of $PGF_2a+PGF_2a+CIDR$ Program on Estrous Response in Holstein with Varying BCS in Early Postpartum (분만후 젖소에 있어서 $PGF_2a+PGF_2a+CIDR$ Program 적용에 의한 발정유기시 BCS의 영향)

  • Baek K. S.;Park S. J.;Park S. B.;Kim H. S.;Lee H. J.;Lee W. S.;Jeon B. S.;Ahn B. S.;Kim J. G.;Jeong G. Y.;Son J. K.
    • Journal of Embryo Transfer
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    • v.20 no.3
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    • pp.279-287
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    • 2005
  • This study was carried out to investigate resumption of ovarian cyclicity and effect of BCS on estrous response by treatment of $PGF_2a+PGF_2a+CIDR$ program on day 40 postpartum in lactating dairy cow. First $PGF_2a$ was given on day 40 postpartum, second $PGF_2a$ was given 14 days apart to cows not-responded to 1st $PGF_2a$ and then CIDR was inserted for 7 days after 5 days in cows not-responded to 2nd $PGF_2a$. The $42.9\%$ of the cows showed more than 1 ng/mL milk progesterone concentration within 10 to 30 days postpartum. About $19\%$ of the cows exhibited more than 1 ng/mL milk pro-gesterone concentration between 31 to 50 days postpartum. However $38.1\%$ of the cows have not shown more than 1 ng/mL milk progesterone up to 50 days postpartum. Estrous response to the treatment of 1 st $PGF_2a$ and 2nd $PGF_2a$ was $47.5\%$ and $52.4\%$, respectively. Combination of 1 st $PGF_2a$ and 2nd $PGF_2a$ was $75\%$ and combination of 1st $PGF_2a$+2nd $PGF_2a$+CIDR was $87.5\%$. Estrous response to the treatment of $PGF_2a+PGF_2a$ program was $61.5\%$ in cows with less than 2.50 BCS and $81.5\%$ in cows with 2.75${\~}$3.50 BCS. Estrous response to the treatment of CIDR was $40\%$ in cows with less than 2.50 BCS and $80\%$ in cows with 2.75${\~}$3.50 BCS. Estrous response to the treatment of PPC on day 40 postpartum was $76.9\%$ in cows with less than 2.50 BCS and $96.3\%$ in cows with 2.75${\~}$3.50 BCS.

Rapid Methods to Distinguish Heterodera schachtii from Heterodera glycines Using PCR Technique (PCR 기법을 이용한 사탕무씨스트선충과 콩씨스트선충의 간이동정)

  • Ko, Hyoung Rai;Kim, Eun Hwa;Kim, Se Jong;Lee, Jae Kook;Lee, Wang Hyu
    • Research in Plant Disease
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    • v.23 no.3
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    • pp.241-248
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    • 2017
  • The purpose of this study was to develop rapid methods for distinguishing between Heterodera schachtii and H. glycines detected from chinese cabbage fields of highland in Gangwon, Korea. To do this, we performed PCR-RFLP and PCR with the primers set developed in this study for GC147, GC408 and PM001 population, H. schachtii, and YS224, DA142 and BC115 population, H. glycines. Eight restriction enzymes generated RFLP profiles of mtDNA COI region for populations of H. schachtii and H. glycines, repectively. As a result, treatment of two restriction enzymes, RsaI and HinfI, were allowed to distinguish H. schachtii from H. glycines based on the differences of DNA band patterns. The primer set, #JBS1, #JBG1 and #JB3R, amplified specific fragments with 277 and 339 bp of H. schachtii, 339 bp of H. glycines, respectively, while it did not amplify fragments from three root-knot nematodes and two root-lesion nematodes. Thus, the primer set developed in this study could be a good method, which is used to distinguish between H. schachtii and H. glycines.

A Low Jitter and Fast Locking Phase-Lock Loop with Adaptive Bandwidth Controller

  • Song Youn-Gui;Choi Young-Shig
    • Journal of information and communication convergence engineering
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    • v.3 no.1
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    • pp.18-22
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    • 2005
  • This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

Distress and Associated Factors in Patients with Breast Cancer Surgery : A Cross-Sectional Study (유방암 수술환자의 디스트레스 및 연관인자 : 단면연구)

  • Lee, Sang-Shin;Rim, Hyo-Deog;Woo, Jungmin
    • Korean Journal of Psychosomatic Medicine
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    • v.26 no.2
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    • pp.77-85
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    • 2018
  • Objectives : This study aimed to investigate the level of distress using the distress thermometer (DT) and the factors associated with distress in postoperative breast cancer (BC) patients. Methods : DT and WHOQOL-BREF (World Health Organization Quality of Life Scale Abbreviated Version) along with sociodemographic variables were assessed in patients undergoing surgery for their first treatment of BC within one week postoperatively. The distress group consisted of participants with a DT score ${\geq}4$. The prevalence and associative factors of distress were examined by descriptive, univariable, and logistic regression analysis. Results : Three hundred seven women were recruited, and 264 subjects were finally analyzed. A total of 173 (65.5%) were classified into the distress group. The distress group showed significantly younger age (p=0.045), living without a spouse (p=0.032), and worse quality of life (QOL) as measured by overall QOL (p=0.009), general health (p=0.005), physical health domain (p<0.000), and psychological health domain (p=0.002). The logistic regression analysis showed that patients aged 40-49 years were more likely to experience distress than those aged ${\geq}60years$ (Odds ratios [OR]=2.992, 95% confidence interval [CI] 1.241-7.215). Moreover, the WHOQOL-BREF physical health domain was a predictive factor of distress (OR=0.777, 95% CI 0.692-0.873). Conclusions : A substantial proportion of patients are experiencing significant distress after BC surgery. It would be expected that distress management, especially in the middle-aged patients and in the domain of physical QOL (e.g., pain, insomnia, fatigue), from the early BC treatment stage might reduce chronic distress.