• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.43-48
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• 2008

This paper presents a design of 8B/10B encoder by the coding table reduction. The proposed encoder has reduced coding table modified disparity control block. Logic simulation and synthesis have been done for the proposed design. After synthesized using Magna CMOS $0.18{\mu}m$ process, the proposed design achieved the operating frequency of 343MHz and chip area of $1886{\mu}m^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Speech Sciences
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• v.10 no.3
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• pp.241-250
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• 2003

In this paper, we implemented the vocoder of variable rate by applying the SOLA-B algorithm to the G.729A to the TMS320C5416 in real-time. This method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. But the method applied to the existed G.729A and SOLA-B algorithm is caused the loss of speech quality in G.729A which is not reflected about length variation of speech. Therefore the proposed method is encoded according as it is modified the structure of LSP quantization table about the length of speech is reduced by using the SOLA-B algorithm. The vocoder of variable rate by applying the G.729A and SOLA-B algorithm is represented the maximum complexity of 10.2MIPS about encoder and 2.8MIPS about decoder in 8kbps transmission rate. Also it is evaluated 17.3MIPS about encoder, 9.9MIPS about decoder in 6kbps and 18.5MIPS about encoder, 11.1MIPS about decoder in 4kbps according to the transmission rate. The used memory is about program ROM 9.7kwords, table ROM 4.69kwords, RAM 5.2kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, the result of MOS test for evaluation of speech quality of the vocoder of variable rate which is implemented in real-time, it is estimated about 3.68 in 4kbps.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.84-89
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• 2003

In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2147-2159
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• 1994

In this parper, the performance of trellis coded DS/SSMA system using feedforward trellis encoder with sasymmetric signal constellation are evaluated over AW(In channel. The numerical results of trellis coded 4 PSK(code rate 1/2)and 8-PSK(code rate2/3) are calculated for 2-state and 4-state cases and compared with those of the Boudreau's system using feedback trellis encoder without optimizing the signal constellation. The method of moments is employed to evaluate the multiple access interference, in conjunction with the generalized transfer function techniques for trellis code. The numerical results show that the proposed system in this paper is always better than the Boudreau's system over AWGN channel; particularly at $P_b:10$, $0.2dB\sim2.4dB$ improvement over AWGN channel are obtained.

• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.1976-1988
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• 1996

This paper describes TCM(trellis coded modulation) schemes using 32VSB signal for digital CATV system. First we design optimum encoder with code rate 4/5 for 32VSB by using one dimenstional signal constellation and obtain 0.75-4.38 dB coding gains over the existing uncoded 16VSB. Second by using two dimensional signal constellation we design TCM encoders with code rate 9/10, which are better in the power efficienty (0.5-2.27 dB) and the transmission rate(12.5%), and we also design TCM encoders which have more coding gains than one dimensional TCM encoders for the larger number of states(more than 8 states).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1513-1526
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• 2009

The SVC (Scalable Video Coding) scheme can be effectively used for reducing the redundancy and for improving the coding efficiency but, it requires very high computational complexities. In order to accelerate the successful standardization and commercialization of the Advanced Terrestrial-DMB service, it is necessary to overcome this problem. For this aim, in this paper, we propose an efficient aggregated encoder control algorithm, which shows better performances than the conventional control scheme. Computer simulation result shows that the proposed scheme performs about up to 0.3dB better than those of the conventional scheme. Additionally, based on this control scheme, we propose a fast mode decision method by constraining the redundant coding modes based on the statistical properties of the quantization parameter in the spatial scalable encoder. Through computer simulations, it is shown that the proposed control schemes reduce the heavy computational burden up to 12% compared to the conventional scheme, while keeping the objective visual qualify very high.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.