8B/10B Encoder Design by Coding Table Reduction
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Shin, Beom-Seok
(Samsung Advanced Institute of Technology)
Kim, Yong-Woo (School of Electronic Engineering & Institute for Information and Electronics Research, Inha University) Yoon, Kwang-Sub (School of Electronic Engineering & Institute for Information and Electronics Research, Inha University) Kang, Jin-Ku (School of Electronic Engineering & Institute for Information and Electronics Research, Inha University) |
1 | A.X.Widmer, "A DC-balanced, Partitioned-Block, 8B/10B transmission Code", IBM J. Res. Develop, vol. 27, pp.440-451, September, 1983 DOI ScienceOn |
2 | Actel, "Implementing an 8b/10b Encoder/Decoder for Gigabit Ethernet", Application Note, Oct, 1998 |
3 | Lattice, "8b/10b Encoder/Decoder" Reference Design, Nov, 2002 |
4 | H. Lee, S. Park, "High speed 8B/10B encoder/decoder design by Logic Reduction", 2003 SoC Design Conf., pp.910-913, Nov, 2003 |
5 | Xilinx, Logic core, 8B/10B Encoder v5.0, May, 2004 |
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