• Title/Summary/Keyword: 7-level H-Bridge Inverter

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Analysis and simulation of Cascaded H-bridge 7 level inverter for eliminating typical harmonic waveforms (특정 고조파 제거를 위한 Cascaded H-bridge 7레벨 인버터의 특성해석 및 시뮬레이션)

  • Jin, Sun-Ho;Oh, Jin-Suk;Jo, Kwan-Jun;Kwak, Jun-Ho;Lim, Myoung-Kyu;Kim, Jang-Mok
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2005.06a
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    • pp.1022-1028
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    • 2005
  • This paper is presented the analysis results and simulation results of cascaded H-bridge 7 level inverter with various modulation index. Stepped waveform having number of switching was used to eliminate harmonic components. Switching angles according to modulation index are calculated numerically. Therefore, 3 times of switching with 7 level topology and QWS(Quarter Wave Symmetry) could eliminate 5th and 7th harmonics. The harmonic characteristics are compared to those of space vector modulation method which known as common modulation method in industrial field. Stepped waveform method showed higher ability to reduce, especially lower order of harmonics.

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Converter Utilization Ratio Enhancement in the THD Optimization of Cascaded H-Bridge 7-level Inverters

  • Khamooshi, Reza;Namadmalan, Alireza;Moghani, Javad Shokrollahi
    • Journal of Power Electronics
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    • v.16 no.1
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    • pp.173-181
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    • 2016
  • In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

A Voltage Control Technique of Line-Interactive DVR Using 7-Level H-Bridge Inverter (7-레벨 H-Bridge 인버터를 이용한 Line-Interactive DVR의 전압제어)

  • Kang, Dae-Wook;Hyun, Dong-Seok;Lee, Woo-Cheol
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.4
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    • pp.705-715
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    • 2007
  • Recently, the interest on power quality has been hot issue because the equipments cause voltage disturbance and have become more sensitive to the voltage disturbance. Additionally, the reseach on power electronic equipments applying to the high power has been increased. This paper deals with Line-Interactive Dynamic Voltage Restorer(LIDVR) system using 7-Level H-Bridge inverter, which is one of the solutions to compensate the voltage disturbance and to increase the power of equipments. The LIDVR has the following advantages comparing to the DVR with the series injection transformer. It has the power factor near to unity under the condition of normal source voltage, can compensate the harmonic current of the load and the instant interruption, and has the fast response. First, the construction, the operation mode and algebraic modeling of LIDVR are reviewed. And then the voltage control algorithm is proposed to get the sinusoidal load voltage with constant amplitude. Finally, simulation and experiment results verify the proposed LIDVR system.

Development of 3,300V 1MVA Multilevel Inverter using Series H-Bridge Cell (3,300V 1MVA H-브릿지 멀티레벨 인버터 개발)

  • 박영민;김연달;이현원;이세현;서광덕
    • The Transactions of the Korean Institute of Power Electronics
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    • v.8 no.6
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    • pp.478-487
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    • 2003
  • In this paper, a type and special feature of Multi-level inverter used in medium-voltage and high-capacity motor driver is introduced. Especially, a power quality and structural advantages of H-Bridge Multi-level inverter is described. It presented the specific structure of power circuit, design method, controller composition and PWM techniques of the cascaded H-Bridge Multi-level inverter which is developed. The feasibility of the developed product based on 3,300V lMVA 7-level H-bridge inverter was studied by experiments and we get conclusion that 1)generate of near-sinusoidal output voltage; 2)is low dv/dt at output voltage; 3)reduce the harmonic injection at input; Experiment demonstrate that it is very economical in productivity because of using the existing production technique and examination equipment, and has the reliability and a good maintenance due to the structure of Power Cell unit combination as well as low cost IGBT.

Output Filler Design for Noise Reduction of Induction Motor Drive System using H-Bridge 7-Level Inverters (H-Bridge 7레벨 인버터를 이용한 유도전동기 구동시스템의 노이즈 저감을 위한 출력 필터설계)

  • Kim, Soo-Hong;Ahn, Young-Oh;Kim, Yoon-Ho;Bang, Sang-Seok;Kim, Kwang-Seob
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.3
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    • pp.36-44
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    • 2006
  • In general, the generated harmonics and noise of the PWM inverter are affected by PWM switching method, switching frequency, dv/dt and di/dt. Since multilevel inverters are often applied to the high power system, and operates with low switching frequency, theyproduce large size of harmonic contents and noise. Thus it is necessary to install output filters in the multilevel inverter. In this paper a filter design approach for the harmonic and noise reduction the three phase induction motor driving system using H-bridge 7-level inverter system is presented. The passive filter that has low cost and simple structure and can effectively reduce harmonics and noise, is designed and applied to the three phase induction motor drive having multilevel inverter system. The designed system is implemented and verified by simulation and experiments.

Voltage Balancing Control of Input Voltage Source Employing Series-connected Capacitors in 7-level PWM Inverter (7-레벨 PWM 인버터의 직렬 커패시터 입력전원의 전압균형제어)

  • Kim, Jin-San;Kang, Feel-soon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.2
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    • pp.209-215
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    • 2018
  • This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

Filtering Techniques to Reduce the Transient Voltage of High Voltage Induction Motor on H-bridge cascaded 7- level Inverte (H-Bridge 7-레벨 인버터 구동시 고압 유도전동기에서 발생하는 과도전압 저감을 위한 필터기술)

  • Kwon, Young-Mok;Kim, Jae-Chul;Kim, Young-Sung;Lee, Yang-Jin
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2005.05a
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    • pp.47-50
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    • 2005
  • In this paper, we investigate a filtering technique to reduce the adverse effect of long motor leads on H-bridge cascaded 7-level inverter fed ac motor drive. The switching surge voltage becomes the major cause to occur the insulation failure by serious voltage stress in the stator winding of high voltage induction motor. However, the effect of switching surge appears un seriousin high voltage induction motor than low voltage induction motor. Consequently, we demonstrated that the filter connected to the motor terminals greatly reduces the transient voltage stress and ringing, moreover we show lowers the dv/dt of the inverter switching pulse. The results of simulation show the suppression of dv/dt and the reduced peak voltage at the motor end of a long cable.

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Development of 3300V 1MVA Multilevel Inverter using Cascaded H-Bridge Cell (3300V 1MVA H-브릿지 멀티레벨 인버터 개발)

  • Park Y.M.;Kim Y.D.;Lee H.W.;Lee S.H.;Seo K.D.
    • Proceedings of the KIPE Conference
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    • 2003.07b
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    • pp.593-597
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    • 2003
  • Multilevel power conversion technology has received increasing attention recently for high power applications. The converters with the technology are suitable for high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and apply for the high voltage equipment with a limited voltage rating of device. In the family of multilevel inverters, the topologies based on cascaded H-bridges are particularly attractive because of their modularity and simplicity of control. This paper presents multilevel inverter with cascaded H-bridge for large-power motor drives. The main features of this drive 1) reduce harmonic injection 2) can generate near-sinusoidal voltages, 3) have almost no common-mode voltage; 4) are low dv/dt at output voltage; 5)do not generate significant over-voltage on motor terminal; The topology of the developed product is presented and the feasibility study of the inverter on 3300v 1MVA 7-level H-bridge type was tarried out with experiments.

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A New Photovoltaic System Architecture of Module-Integrated Converter with a Single-sourced Asymmetric Multilevel Inverter Using a Cost-effective Single-ended Pre-regulator

  • Manoharan, Mohana Sundar;Ahmed, Ashraf;Park, Joung-Hu
    • Journal of Power Electronics
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    • v.17 no.1
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    • pp.222-231
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    • 2017
  • In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

  • Tarmizi, Tarmizi;Taib, Soib;Desa, M.K. Mat
    • Journal of Power Electronics
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    • v.19 no.5
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    • pp.1074-1086
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    • 2019
  • This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.