• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.9 s.339
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• pp.41-48
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• 2005

In this paper, we suggest the scheme combining long-term feedback and short-term feedback in MIMO multi-user system and analyze its system performance. At the beginning of communication, long-term feedback is fed back to transmitter such as the number of active antennas, constellations, and transmission powers which are determined to satisfy the given target symbol error and target data rate for each user. After this, short-term feedback of active antenna index is fed back periodically Simulation results show the proposed scheme outperforms better than long-term feedback or short-term feedback information scheme.

• Journal of the Korean Vacuum Society
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• v.11 no.1
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• pp.35-42
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• 2002

We fabricate thermally stable and low resistance Ru ohmic contacts to $n-ZnO:Al(3\times10^{18}\textrm{cm}^{-3})$, grown by specially designed dual target sputtering system. It is shown that the as-deposited Ru contact produces a specific contact resistance of $2.1{\times}10^{-3}{\Omega}\textrm{cm}^2$. Annealing of the Ru contacts leads to the improvement of current-voltage characteristics. For example, annealing of the contact at $700^{\circ}C$ for 1 min produces a contact resistance of $3.2{\times}10^{-5}}{\Omega}\textrm{cm}^2$. furthermore, the metallisation scheme is found to be thermally stable: the surface of the contact is fairly smooth with a rms roughness of 1.4 nm upon annealing at $700^{\circ}C$. These results strongly indicate that the Ru contact represents a suitable metallisation scheme for fabrication of high-performance ZnO-based optical devices and high-temperature devices. In addition, possible mechanisms are suggested to describe the annealing temperature dependence of the specific contact resistance.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.36-42
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• 2010

This paper describes a multi channel measurement system which can measure the cellular respiration level in a solution containing cells by using a Clark-type sensor with the solution temperature control unit. The Clark-type sensor can measure the cellular respiration level in the solution because it can measure the reduction current depending on the dissolved oxygen level in the solution. This measurement system was maintained the temperature within ${\pm}0.1^{\circ}C$ of the setting temperature value by on/off control method in order to measure the precise cellular respiration level. The measurement system showed that the applied voltage to the working electrode was very stable(-0.8 V$\pm$ 0.0071 V) by using proportional control method. From the current measurement, the response time and the linearity correlation coefficient were 25 sec and 0.94, respectively, which are very close to the results of the commercial product. Using this system and the fabricated Clarktype sensor, the average ratio of the uncoupled OCR(oxygen consumption rate) to the coupled OCR was 1.35 and this is almost the same as that obtained from a commercial systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.27-36
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• 2005

This paper presents an area-efficient architecture to implement the high-speed Reed-Solomon(RS) decoder, which is used in a variety of communication systems such as wireless and very high-speed optical communications. We present the new pipelined-recursive Modified Euclidean(PrME) architecture to achieve high-throughput rate and reducing hardware-complexity using folding technique. The proposed pipelined recursive architecture can reduce the hardware complexity about 80$\%$ compared to the conventional systolic-array and fully-parallel architecture. The proposed RS decoder has been designed and implemented with the 0.13um CMOS technology in a supply voltage of 1.2 V. The result show that total number of gate is 393 K and it has a data processing rate of S Gbits/s at clock frequency of 625 MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• The Journal of Korean Academy of Prosthodontics
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• v.42 no.5
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• pp.544-555
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• 2004

Statement of problem: Shade selection has traditionally been accomplished by visual examination, which is particularly relevant to the shade selection of anterior teeth, but the subjective nature of visual analysis can lead to errors in shade matching. Recently shade selection systems have been developed to provide a more objective and scientific approach to understanding and clarifying shade selection. Purpose : The purpose of this study was analysis of various shade analyzing equipment with the goal of providing a more objective shade selection. Materials and method: Visual shade matching system selection(Vita Lumin Vacuum shade guide, Vitapan 3D Master shade guide) and mechanical shade matching method($ShadeEye^{(R)}$-EX Chroma Meter, $Shadescan^{TM}$ System) used for this study. The shade guide tap specimens for 10 extracted maxillary anterior teeth were produced by selecting shades using each shade matching system. The accuracy of the selection of shades for the teeth and fabricated specimens were evaluated by analyzing the calculated shade difference(${\Delta}E^*$), using a spectrophotometer and calculating the output of value $L^*,\;a^*,\;b^*$. Results and conclusion: The results show that the average ${\{Delta}E^*$ value (difference of shade) of the shade tap specimens to the actual specimen decreased in the following order: Vita Lumin Vacuum Shade Guide(VL), $ShadeEye^{(R)}$-EX Chroma Meter(SE) Vitapan 3D Master Shade guide(V3), and $Shadescan^{TM}$ System(55) : and that there are significant statistical differences between the VL and SS (p<0.05). In the analysis of the ${\Delta}E^*$ (difference of shade) value,40% of the VL group was found to be less than 3.3 (limit value of shade tap specimens clinically acceptable), 60% in the V3 group, 50% in the SE group, and 80% in the SS group.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.39-42
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• 2018

In this paper, a low-power MPPT interface circuit for vibration energy harvesting sources is presented. The designed circuit rectifies the harvested ac type energy to the dc type energy required to drive the system, and periodically samples and holds the open circuit voltage (Voc) through the MPPT controller, and transfers the harvested power to the load while maintaining the input voltage at 1/2 of the maximum available power point. All circuits have been designed using a 0.35-um CMOS technology, and the operation has been verified through simulation. Simulation results show that the designed circuit consumes 98nA of current at 3V input voltage and the maximum power efficiency is 99.21%. The designed chip occupies $1.281mm{\times}1.236mm$.

• The Journal of Korean Society for Radiation Therapy
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• v.32
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• pp.61-71
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• 2020

Purpose: To investigate the effect of collimator angle on plan quality of PAN-Pelvis Multi-isocenter VMAT plan, dose reproducibility at the junction and impact on set-up error at the junction. Material and method: 10 adult patients with whole pelvis cancer including PAN were selected for the study. Using Trubeam STx equipped with HD MLC, we changed the collimator angle to 20°, 30°, and 45° except 10° which was the default collimator angle in the Eclipse(version 13.7) and all other treatment conditions were set to be the same for each patient and four plans were established also. To evaluate these plans, PTV coverage, coverage index(CVI) and homogeneity index (HI) were compared and clinical indicators for each treatment sites in normal tissues were analyzed. To evaluate dose reproducibility at the junction, the absolute dose was measured using a Falmer type ionization chamber and dose changes at the junction were evaluated by moving the position of the isocenter in and out 1~3mm and setting up the virtual volume at the junction. Result: CVI mean value was PTV-45 0.985±0.004, PTV-55 0.998±0.003 at 45° and HI mean value was PTV-45 1.140±0.074, and PTV-55 1.031±0.074 at 45° which were closest to 1. V20Gy of the kidneys decreased by 9.66% and average dose of bladder and V30 decreased by 1.88% and 2.16% at 45° compared to 10° for the critical organs. The dose value at the junction of the plan and the actual measured were within 0.3% and within tolerance. At the junction, due to set-up error the maximum dose increased to 14.56%, 9.88%, 8.03%, and 7.05%, at 10°, 20°, 30°, 45°, and the minimum dose decreased to 13.18%, 10.91%, 8.42%, and 4.53%, at 10°, 20°, 30°, 45° Conclusion: In terms of CVI, HI of PTV and critical organ protection, overall improved values were shown as the collimator angle increased. The impact on set-up error at the junction by collimator angle decreased as the angle increased and it will help improve the anxiety about the set up error. In conclusion, the collimator angle should be recognized as a factor that can affect the quality of the multi-isocenter VMAT plan and the dose at the junction, and be careful in setting the collimator angle in the treatment plan.