• The KIPS Transactions:PartB
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• v.11B no.4
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• pp.395-402
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• 2004

In this paper, we proposed a new method of the large capacity steganography using adaptive threshold on bit planes. Applying fixing threshold, if we insert information into all bit planes, all bit planes showed different image quality. Therefore, we first defined the bit plane weight to solve the fixing threshold problem. We then proposed a new adaptive threshold method using the bit plane weight and the average complexity to increase insertion capacity adaptively. In the experiment, we inserted information into the standard images with the same image quality and same insertion capacity, and we analyzed the insertion capacity and image duality. As a result, the proposed method increased the insertion capacity of about 6% and improved the image quality of about 24dB than fixed threshold method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.777-780
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• 2005

모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.753-760
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• 2012

This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of "01111110". When data bit stream consist of the consecutive 5-bit "1" after "0", the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits "1" after "0" in the input data stream, inserts violently the "0" after 5th "1" of the consecutive 5-bit "1" after "0". As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits "1" after "0" when the code is given to each characters.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.47-56
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• 2004

This paper describes a new bit allocation algorithm that can achieve a constant bit rate when coding multiple video objects, while improving rate-distortion (R-D) performance over the VM5 method for MPEG-4 object-based video coding. In particular, we propose two models to estimate the rate-distortion characteristics of coded objects as well as skipped objects. Based on the proposed models, we present several R-D coding modes with spatio-temporal trade-offs to improve coding efficiency. The proposed algorithm is performed at the object level for object-based video coding. Simulation results demonstrate moderate improvement at low as well as high bit rates. The proposed algorithm can produce the actual coded bits very close to the target bits over a wide range of bit rates. Consequently, the proposed algerian has not experienced any buffer overflow or underflow over the bit rates between 32 kbps and 256 kbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.3
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• pp.461-470
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• 1999

This paper presents the description of a 4-bit digital p-i-n diode phase shifter that was designed for quasimillimeter wave band satellite receiver to use in phased-array systems. 180$^{\circ}$ and 90$^{\circ}$ cells are designed in reflection type that consists of a 3-dB rat-race hybrid coupler, 45$^{\circ}$ and 22.5$^{\circ}$ cells are designed in loaded-line type to reduce the size of circuit and the number of diode to be used. The 4-bit phase shifter uses eight p-i-n diodes mounted in the microstrip circuit. The average insertion loss for the 16 phase states is 6.92dB over the 19.8~20.3 GHz band and maximum phase error is 6.2$^{\circ}$ at 20 GHz.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.714-725
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• 1997

This paper proposes an image compression method using the wavelet transform and bit-plane coding of wavelet coefficients. The hierarchical application of wavelet transform to an image produces one low resoluation(the subband with lowest frequency) image and several high frequency subbands. In the proposed method, the low resolution image is compressed by a lossless method at 8 bits per each coefficient. However, the high frequency subbands are decomposed into 8 bit planes. With an adptive block coding method, the decomposed bit planes are effectively compressed using localized edge information in each bit plane. In addition, the propsoed method can control bit rates by selectively eliminating lessimportant subbands of low significant bit planes. Experimental results show that the proposed scheme has better performance in the peak signal to noise ratio (PSNR) and compression rate than conventional image coding methods using the wavelet transform and vector quantization.

• The Journal of the Acoustical Society of Korea
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• v.15 no.6
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• pp.59-65
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• 1996

This paper proposes a 4 kbps PSI-VSELP(Pitch Synchronous Innovation-Vector Sum Excited Linear Prediction) speech coder which produces speech equivalent to that of the conventional 4.8 kbps VSELP. Since the 'half-rate' is differently defined from country to country, there may be a need to reduce the bit rate of conventional half-rate coder. To minimize the degradation of speech quality caused by bit-rate reduction, it is desirable to perform bit-allocation based on the carefull consideration of the effect of various transmission parameters. This paper adopts this analytical approach for bit-allocation at 4 kbps. To improve the quality of the VSELP coder at 4 kbps, basis vectors which play the most important role in the performance, are optimized by an iterative closed-loop training process and the PSI technique is employed in the VSELP performance, are optimized by an iterative closed-loop training process and the PSI technique is employed in the VSELP coder. To demonstrate the performance of the proposed speech coder, we peformed experiments under the noiseless and error free conditions. From experimental results, even though the proposed 4 kbps PSI-VSELP coder showed lower scores in the objective measure, higher scores in subjective measure was obtained compared with those of the conventional 4.8 kbps VSELp.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.516-521
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• 2022

In this paper, a compact 4-bit chipless RFID(radio frequency identification) tag using a modified ELC(electric field-coupled inductive-capacitive) resonator and multiple slot resonators is proposed. The modified ELC resonator uses an interdigital-capacitor structure in the conventional ELC resonator to lower the resonance peak frequency of the RCS. The multiple slot resonators are designed by etching three slots with different lengths into an inverted U-shaped conductor. The resonant peak frequency of the RCS for the modified ELC resonator is 3.216 GHz, whereas those of the multiple slot resonators are set at 4.122 GHz, 4.64 GHz, and 5.304 GHz, respectively. The proposed compact four-bit tag is fabricated on an RF-301 substrate with dimensions of 50 mm×20 mm and a thickness of 0.8 mm. Experiment results show that the resonant peak frequencies of the fabricated four-bit chipless RFID tag are 3.285 GHz, 4.09 GHz, 4.63 GHz, and 5.31 GHz, respectively, which is similar to the simulation results with errors in the range between 0.78% and 2.16%.