• Journal of Internet Computing and Services
• /
• v.14 no.4
• /
• pp.25-33
• /
• 2013

The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the 4-Bit Pattern Slot Allocation(4-BPSA) algorithm for the high-speed identification of the multiple tags. The proposed algorithm is based on the tree algorithm using the time slot and identify the tag quickly and efficiently through accurate prediction using the a slot as a 4-bit pattern according to the slot allocation scheme. Through mathematical performance analysis, We proved that the 4-BPSA is an O(n) algorithm by analyzing the worst-case time complexity and the performance of the 4-BPSA is improved compared to existing algorithms. In addition, we verified that the 4-BPSA is performed the average 0.7 times the query per the Tag through MATLAB simulation experiments with performance evaluation of the algorithm and the 4-BPSA ensure stable performance regardless of the number of the tags.

• Journal of Korean Tunnelling and Underground Space Association
• /
• v.3 no.4
• /
• pp.17-24
• /
• 2001

Four road tunnels of which the construction conditions were similar were selected in the paper, and laboratory tests and rockmass classification for the tunnels were carried out. And the analysis was performed to find out the correlation between ratio of bit abrasion or drilling parameter and support pattern of tunnel using jumbo drill machine. It was analyzed that there was average abrasion of bit from 11.85% to 3.25% per support patterns of tunnel in four tunnels. Drilling parameter happens to fluctuate according to extent of fracture zone.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.19 no.4
• /
• pp.492-499
• /
• 2016

Null pattern synthesis method using the Quantum-inspired Evolutionary Algorithm(QEA) is described in this study. A $12{\times}12$ planar array antenna is considered and each element of the array antenna is controlled by 6-bit phase shifter. The maximum number of iteration of 500 is used in simulation and the rotation angle for updating Q-bit individuals is determined to make the individual converge to the best solution and is summarized in a look-up table. In this study we showed that QEA can satisfactorily synthesize the null pattern using smaller number of individuals compared with the conventional Genetic Algorithm.

• Journal of Korea Multimedia Society
• /
• v.3 no.4
• /
• pp.372-379
• /
• 2000

In this paper, we propose a fast variable-size block matching algorithm for motion estimation based on bit-pattern. Motion estimation in the proposed algorithm is performed after the representation of image sequence is transformed 8bit pixel values into 1bit ones depending on the mean value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating an unnecessary searching of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides better performance-0.5dB PSNR improvement-than full search block matching algorithm with a fixed block size.

• Journal of Korea Multimedia Society
• /
• v.4 no.5
• /
• pp.390-395
• /
• 2001

In this paper, we propose a fast warping prediction using bit-pattern for motion estimation. Because of the spatial dependency between motion vectors of neighboring node points carrying motion information, the optimization of motion search requires an iterative search. The computational load stemming from the iterative search is one of the major obstacles for practical usage of warping prediction. The motion estimation in the proposed algorithm measures whether the motion content of the area is or not, using bit-pattern. Warping prediction using the motion content of the area make the procedure of motion estimation efficient by eliminating an unnecessary searching. Experimental results show that the proposed algorithm can reduce more 75% iterative search while maintaining performances as close as the conventional warping prediction.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.4
• /
• pp.34-42
• /
• 1981

A 512-bit Task Programmable ROM has been designed and fabricated using PMOS technology. The content of the memory was written through the gate pattern during the fabrication process, and was checked by displaying the output of the chip on an oscilloscope with 512(32$\times$16) matrix points. The operation of the chip was surcessful with operating voltage from -6V to -l2V, The power consumption and propagation delay time have been measured to be 3mW and 13 $\mu$sec, respectively at -6 Volt. The power consunption increased to 27mW and propagation delay time decreased to 3$\mu$sec at -12V. The output of the chip was capable of driving the input of a TTL gate directly and retained a high impedence state when the chip solect function disabled the output.

• Transactions on Electrical and Electronic Materials
• /
• v.3 no.3
• /
• pp.1-7
• /
• 2002

The developed patterns by direct writing of electron beam are measured by AFM, FESEM and optical profiler of WYKO NT3300. From different measurement methods, the measured linewidths of the patterns are shown a little bit wider than designed pattern size due to electrons scattering effect during direct writing of electron beam. The optimized conditions of these experiments are suggested and explained for the forming of structures below 0.1 ㎛ dimension size. Because of electron scattering effects from the different under layers such as Si, Si$_3$N$_4$ and aluminum, the developed pattern size is also influenced by the accelerated energy of electrons, dose, resist and soft and hard bake conditions in PMMA. The distributions of electron beam and calculations of backscattering coefficient are demonstrated by Monte Carlo simulation. From the measured results, the developed linewidth of PMMA/Al /silicon is shown a little bit wider than that of PMMA/Si$_3$N$_4$/silicon structure due to the backscattering effects.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.405-414
• /
• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Progress in Superconductivity
• /
• v.6 no.1
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Journal of Magnetics
• /
• v.6 no.4
• /
• pp.109-118
• /
• 2001

A computer simulation, utilizing the Landau-Lifshitz-Gilbert equation, of ultra-high- density recording on continuous longitudinal media is carried out. The two important features of this work are the use of a planar-type head, which enables a high write field of 14183 Oe ts be generated at the center of the recording medium, and the media with very high coercivities up to 13010 Oe. From a systematic investigation, it is found that the optimum write field is higher than the medium coercivity by only 3400 Oe over a wide coercivity range. This new finding allows one to write an a medium with a very high coercivity by using a planar-type head. It is demonstrated that a reasonably good bit pattern with a bit density of 605 kfci is generated on the medium with a coercivity of l1720 Oe, and, combined with a high track pitch density of 100 ktpi, a recording density of 60 Gb/in$^2$can be obtained in a single layer medium. With an improved write- head designs even a higher recording density of 75 Gb/in$^2$may be possible since comparison of the results for the bit pattern from the present head profile and the ideal Lindholm profile indicates an increase in the track pitch density of about 27%. Even at this density, the thermal stability parameter (KV/kT) at room temperature is high enough (60) to provide ample room for thermal stability.