• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.16 no.3
• /
• pp.1-8
• /
• 2017

Tool path generation is a part of process planning in 3D printing. This is done before actual printing by a computer rather than an AM machine. The mesh geometry of the 3D model is sliced layer-by-layer along the Z-axis and tool paths are generated from the sliced layers. Each 2-dimensional layer can have two types of printing paths: (i) shell and (ii) infill. Shell paths are made of offset loops. During shell generation, twists can be produced in offset loops which will cause twisted tool paths. As a twisted tool path cannot be printed, it is necessary to remove these twists during process planning. In this research, An algorithm is presented to remove twists from the offset loops. To do so the path segments are traversed to identify twisted points. Outer offset loops are represented in the counter-clockwise segment order and clockwise rotation for the inner offset loop to decide which twisted loop should be removed. After testing practical 3D models, the proposed algorithm is verified to use in tool path generation for 3D printing.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.3
• /
• pp.18-27
• /
• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• Journal of the Society of Naval Architects of Korea
• /
• v.56 no.1
• /
• pp.66-74
• /
• 2019

In the field of shipbuilding design, the use of 3D CAD is becoming commonplace, and most of the large shipyards are conducting 3D design. However at the production site, workers are still working on 2D drawings rather than 3D models. This tendency is even worse in small-scale shipyards and block manufacturing shops. Particularly, in a manufacturing shop that is engaged in the outsourcing of blocks, it may not be possible to provide 3D model. However, the demand for 3D models in the production field is steadily increasing. Therefore, it would be helpful if 3D model could be generated from a 2D drawing. In this paper, we propose a method to extract template and unfolded surface shape information from shell template offset drawing using computer vision technology. Also a 3D surface model was reconstructed and visualized from the extracted information. The result of this study is thought to be helpful in the work environment where 3D model information can not be obtained.

• Journal of Fashion Business
• /
• v.20 no.4
• /
• pp.153-171
• /
• 2016

With the advent of smart clothing for health care and sports, the sophisticated designs with curved seams are drawing attention. One of the problems in those clothing is to determine the design curves in 2D pattern, such that it corresponds to the lines on the intended 3D body. Moreover, the difficulty increases when the original pattern needs to be changed for various sizes and body types. We compare two methods of pattern enlargement in this paper: one is the offset/projection type, and the other is the split grading type. For the enlarged pattern with offset/projection type, the 3D surface offset was first adopted to transform the standard lower body to the target larger size; next, the design lines were projected to the new 3D surface, following which the 3D pattern was developed from the newly transformed 3D surface. In the second method, the enlarged pant patterns were developed by the split grading method. Here, a 3D pattern was developed from the initial body, and then enlarged to the target size by the conventional split grading method. Two feminine pants patterns were examined by 3D virtual fitting. We observed that the 3D offset/projection pants pattern was well fitted, having an evenly distributed surplus, as compared with the sample developed using the split grading method. The difference between the two patterns were apparent at the location where several curved lines merged.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.268-272
• /
• 2001

In this thesis, PLVCO(Phase Locked Voltage Controlled Oscillator) using 24.42 GHz voltage controlled hair-pin resonator oscillator, Sequency divider, buffer amplifier, -10 dB directional coupler and phase detector is designed and fabricated for B-WLL. The PLVCO shows the oscillator output power of 16.5 dBm at 24.42 GHz, and phase noise of -76.3 dBc/Hz at 1001:Hz offset, -72.8dBc/Hz at 10 kHz offset from fundamental frequency.

• International Journal of Internet, Broadcasting and Communication
• /
• v.15 no.3
• /
• pp.122-128
• /
• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• Korean Journal of Computational Design and Engineering
• /
• v.3 no.2
• /
• pp.127-134
• /
• 1998

This paper presents d new algorithm to compute the offlet curve of a given planar parametric curve. We reduce the problem of computing an offset curve to that of intersecting a surface to a paraboloid. Given an input curve C(t)=(x(t), y(t))∈R², the corresponding surface D/sub c(t)/ is constructed symbolically as the envelope surface of a one-parameter family of tangent planes of the paraboloid Q:z=x²+y²along a lifted curve C(t)=(x(t), y(t), x(t)²+y(t)²∈Q. Given an offset distance d∈R, the offset curve C/sub d/(t) is obtained by the projection of the intersection curve of D/sub c(t)/ and a paraboloid Q:z=x²+y²-d² into the xy-plane.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.4
• /
• pp.684-691
• /
• 2001

In this paper, the BER performance of OFDM/M-ary PSK systems is analyzed with considering carrier-frequency offset and TCM technique, which encodes and modulations simultaneously, is adopted to OFDWM-ary PSK systems for compensation of performance degradation according to carrier-frequency offset. As a result of analysis, the error performance of OFDM/M-ary PSK systems is degraded as the frequency offset is increased. And the frequency offset should be below 0.025 in order to achieve $BER= 10^{-3}$ with $E_b/N_o$ of 10 dB. Especially, when the TCM technique is adopted to OFDM/M-ary PSK systems, the performance improvement of about 4 dB is obtained in terms of $E_b/N_o$.

• Journal of Korean Institute of Industrial Engineers
• /
• v.19 no.3
• /
• pp.123-137
• /
• 1993

In this paper, an integrated approach is proposed to generate gouging-free Cartesian tool paths for machining sculptured surfaces from 3D measurement data. The integrated CAD/CAM system consists of two modules : offset surface module an Carteian tool path module. The offset surface module generates an offset surface of an object from its 3D measurement data, using an offsetting method and a surface fitting method. The offsetting is based on the idea that the envelope of an inversed tool generates an offset surface without self-intersection as the center of the inversed tool moves along on the surface of an object. The surface-fitting is the process of constructing a compact representation to model the surface of an object based on a fairly large number of data points. The resulting offset surtace is a composite Bezier surface without self-intersection. When an appropriate tool-approach direction is selected, the tool path module generates the Cartesian tool paths while the deviation of the tool paths from the surface stays within the user-specified tolerance. The tool path module is a two-step process. The first step adaptively subdivides the offset surface into subpatches until the thickness of each subpatch is small enough to satisfy the user-defined tolerance. The second step generates the Cartesian tool paths by calculating the intersection of the slicing planes and the adaptively subdivided subpatches. This tool path generation approach generates the gouging-free Cartesian CL tool paths, and optimizes the cutter movements by minimizing the number of interpolated points.

• Journal of electromagnetic engineering and science
• /
• v.8 no.3
• /
• pp.134-137
• /
• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.