• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of Power Electronics
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• v.15 no.3
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• pp.644-651
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• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.936-943
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• 2003

The miniaturized wireless endoscope consists of CMOS Image sensor, FPGA, LED, Battery, DC to DC Converter, Antenna and Transmitter. FSK transmitter is designed and fabricated with 10 mm(diameter)${\times}$23 mm(thickness) dimension considering the maximum permission exposure(MPE), system size, power consumption, linearity and modulation method. Experimental results is - 3.67 dBm output power level, 20 MHz frequency deviation, and - 99 dBc/Hz(@100 kHz offset) phase noise at 1.2 GHz. From the in-vivo experiment, the designed FSK transmitter has a acceptable capability for wireless endoscope.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.895-898
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• 2002

In this paper, we propose a 3D image player for LCD monitors as well as CRT monitors. As we consider an afterglow and digital processing of LCD monitors, a stereoscopic images can be shown on CRT monitors as well as LCD monitors using the proposed a3D image player. We have implemented a 3D image player using FPGA (MAX 9320), We show prove that a stereoscopic images are shown on the LCD monitors.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.335-343
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• 2024

Real-time target signal processing techniques for FMCW LiDAR are described in this paper. FMCW LiDAR is gaining attention as the next-generation LiDAR for self-driving cars because of its detection robustness even in adverse environmental conditions such as rain, snow and fog etc. in addition to its long range measurement capability. The hardware architecture which is required for high-speed data acquisition, data transfer, and parallel signal processing for frequency-domain signal processing is described in this article. Fourier transformation of the acquired time-domain signal is implemented on FPGA in real time. The paper also details the C-FAR algorithm for ensuring robust target detection from the transformed target spectrum. This paper elaborates on enhancing frequency measurement resolution from the target spectrum and converting them into range and velocity data. The 3D image was generated and displayed using the 2D scanner position and target distance data. Real-time target signal processing and high-resolution image acquisition capability of FMCW LiDAR by using the proposed parallel signal processing algorithms based on FPGA architecture are verified in this paper.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.402-404
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• 1997

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implements the ray tracing with software and hardware. Specially we designs the hit-test unit with FPGA tool for the ray-tracing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.73-82
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• 2014

The LM algorithm is used in solving the least square problem in a non linear system, and is used in various fields. However, in cases the applied field's target functionis complicated and high-dimensional, it takes a lot of time solving the inner matrix and vector operations. In such cases, the LM algorithm is unsuitable in embedded environment and requires a hardware accelerator. In this paper, we implemented the LM algorithm in hardware. In the implementation, we used pipeline stages to divide the target function operation, and reduced the period of data input of the matrix and vector operations in order to accelerate the speed. To measure the performance of the implemented hardware, we applied the refining fundamental matrix(RFM), which is a part of 3D reconstruction application. As a result, the implemented system showed similar performance compared to software, and the execution speed increased in a product of 74.3.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1424-1433
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• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.