Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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FPGA Implementation of Levenverg-Marquardt Algorithm

LM(Levenberg-Marquardt) 알고리즘의 FPGA 구현

  • Lee, Myung-Jin (Department of electronics and communication engineering, Kwangwoon University) ;
  • Jung, Yong-Jin (Department of electronics and communication engineering, Kwangwoon University)
  • 이명진 (광운대학교 전자통신공학과) ;
  • 정용진 (광운대학교 전자통신공학과)
  • Received : 2014.06.12
  • Accepted : 2014.10.27
  • Published : 2014.11.25
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Abstract

The LM algorithm is used in solving the least square problem in a non linear system, and is used in various fields. However, in cases the applied field's target functionis complicated and high-dimensional, it takes a lot of time solving the inner matrix and vector operations. In such cases, the LM algorithm is unsuitable in embedded environment and requires a hardware accelerator. In this paper, we implemented the LM algorithm in hardware. In the implementation, we used pipeline stages to divide the target function operation, and reduced the period of data input of the matrix and vector operations in order to accelerate the speed. To measure the performance of the implemented hardware, we applied the refining fundamental matrix(RFM), which is a part of 3D reconstruction application. As a result, the implemented system showed similar performance compared to software, and the execution speed increased in a product of 74.3.

LM 알고리즘은 비선형 시스템의 least square problem을 풀기위해 사용되는 것으로, 다양한 분야에서 활용되고 있는 중요한 알고리즘이다. 하지만 응용 분야의 목적 함수가 복잡하고 고차원인 경우, 목적 함수의 연산 횟수가 많아지고, 내부에서 연산되는 행렬 및 벡터 연산에 시간이 많이 소요되어, 임베디드 환경에서의 실시간 동작을 위해서는 하드웨어 가속기 설계가 불가피하다. 본 논문에서는 LM 알고리즘을 하드웨어로 설계하였으며, 반복되는 목적 함수 연산을 파이프라인 처리 하고, 행렬 및 벡터 연산은 데이터 입력 주기를 줄여 속도를 향상시켰다. 설계한 LM 알고리즘의 하드웨어 성능을 측정하기 위해, 응용분야로 3D reconstruction의 한 부분인 refining fundamental matrix(RFM)를 적용하였다. 실험 결과 소프트웨어와 비슷한 정확도를 가지면서, 최대 74.3배의 속도 향상을 볼 수 있었다.

Keywords

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