• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.89-110
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• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• ETRI Journal
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• 제33권6호
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제4권2호
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• pp.41-46
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• 2015

컴퓨터 사용 환경이 모바일 시장 및 소형 전자기기 시장 등으로 다양해짐에 따라 저전력 고성능 시스템에 대한 요구도 커지고 있다. 3차원 die-stacking 기술은 한정된 공간에서 DRAM의 집적도과 접근 속도를 높여 차세대 공정방식으로 많은 연구가 되고 있다. 이 논문에서는 3차원 구조의 DRAM 로직층에 재구성형 가속기를 구현하여 저전력 고성능 시스템을 구성하는 방법을 제안한다. 또한 재구성형 가속기의 지역 메모리로 캐시를 적용하고 활용하는 방법에 대해서 논의한다. DRAM의 로직층에 재구성형 가속기를 구현할 경우 위치적인 특성으로 데이터 전송 및 관리에 필요한 비용이 줄어들어 성능을 크게 향상시킬 수 있다. 제안된 시스템에서는 최대 24.8의 스피드업을 기록하였다.

• 한국재료학회지
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• 제13권7호
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• pp.478-483
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• 2003

The crystallographic characteristics of the $(Bi, La)_4$$Ti_3$$O_{12}$ thin film, which is considered as an applicable dielectrics in the ferroelectric RAM device due to a low crystallization temperature and a good fatigue property, were investigated at the atomic scale by high resolution transmission electron microscopy and the high resolution Z-contrast technique. The analysis showed that a (00c) preferred orientation and a crystallization of the film were enhanced with the diffraction intensity increase of the (006) and (008) plane as the annealing temperature increased. It indicated a change of the atomic arrangement in the (00c) plane. Stacking faults on the (00c) plane were also observed. Through the comparison of the high-resolution Z-contrast image and the $Bi_4$$Ti_3$$O_{12}$ atomic model, it was evaluated that the intensity of the Bi atom was different according to the atomic plane, and it was attributed to a substitution of La atom for Bi at the specific atom position.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• 한국컴퓨터정보학회논문지
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• 제26권11호
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• pp.1-9
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• 2021

3D-NAND 플래시 메모리는 평면적 구조인 2D-NAND 셀을 적층하는 방식으로 단위 면적당 고용량을 제공한다. 하지만 적층 공정의 특성상 각 레이어별 또는 물리적인 셀 위치에 따라 오류 발생 빈도가 달라질 수 있는 문제가 있다. 이와 같은 현상은 플래시 메모리의 쓰기/지우기(P/E) 횟수가 증가할수록 두드러진다. SSD와 같은 대부분의 플래시 기반 저장장치는 오류 교정을 위하여 ECC를 사용한다. 이 방법은 모든 플래시 메모리 페이지에 대하여 고정된 데이터 보호 강도를 제공하므로 물리적 위치에 따라 오류 발생률이 각기 다르게 나타나는 3D NAND 플래시 메모리에서는 한계를 보인다. 따라서 본 논문에서는 오류 발생률 차이를 보이는 페이지와 레이어를 K-means 머신러닝 알고리즘을 통해 군집으로 분류하고, 각 군집마다 차별화된 데이터 보호강도를 적용한다. 본 논문에서는 페이지와 레이어별로 오류 발생률이 현저하게 달라지는 내구성 테스트가 끝난 시점에서 측정된 오류 발생 횟수를 바탕으로 페이지와 레이어를 분류하고 오류에 취약한 영역에 대해서는 스트라이프에 패리티 데이터를 추가하여 차별화된 데이터 보호 강도 제공을 예시로 보인다. 본 논문에서는 기존의 ECC 또는 RAID 방식의 데이터 보호 구조와 비교하여 제안하는 차별화된 데이터 보호정책이 3D NAND 플래시 메모리의 신뢰성과 수명향상에 기여할 수 있음을 보인다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).