• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.362-362
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• 2010

Today, vast attention has been paid to periodic arrays of nanostructures due to their potential for applications such as memory with huge storage density. Such application requires large-scale fabrication of well ordered nano-sized structures. One of the most widely used methods for the ordered nanostructures is lithography. This top-down process, however, has the limit to reduce size. Here the promising alternative is the self-organization of ordered nano-sized structures such as large scale 2d carbon-induced reconstructions on W(110). In the present study, we report on the first well-resolved atomic resolution STM studies of the well-known R($15{\times}3$) and R($15{\times}12$) carbon induced reconstruction of the W(110). From the atomic image of R($15{\times}3$) for different values of tunneling gap resistance, we can tell there are no missing atoms in unit cells of R($15{\times}3$) and some atomic displacements are substantial from the clean W(110), even though not all the imaged position of atoms correspond to tungsten, but may include those of carbon. We are considering two cases; First case is related to lattice deformation, or top layer of W(110) is deformed in the process of relief of strain caused by random inserting of carbon atoms possibly in the interstitial position. In the second case, R($15{\times}3$) unit cell results from a coincidence lattice between clean W(110) substrate and tungsten carbide overlayer which has rectangular atomic arrangement and giving R($15{\times}3$) coincidence lattice. beta-W2C showing rectangular unit cell should be a candidate. Further, we report on new reconstructions. Unlike the well-known R($15{\times}12$) consisting of two parts, two inner structures between two "Backbone" structures. The new reconstruction, which we found for the first time, contains more parts between the "Backbone"s. Sometimes we can observe the reconstruction consists of only inner parts without "Backbone" parts. Thus, the observed reconstruction can be built by constructing of two types of "Lego"-like block. Moreover, the rectangle shape of "Backbone" transform to parallelogram-like shape over time, the so-called wavy-R($15{\times}12$). Adsorption of hydrogen can be the reason for this transformation.

• The Journal of the Convergence on Culture Technology
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• v.7 no.4
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• pp.113-122
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• 2021

This study begins on the basis of Jacques Lacan's article 『Logical Time and Assertions of Preemptive Certainty: A New Sophism』 published in the reissue of 『Art Note Les Cahiers d'Art』 in March 1945. In this paper, a guard presents an esoteric problem to three prisoners. If the problem is solved, the prisoner is released. A condition is given to solve a problem. Conversation between prisoners is prohibited, and the disc behind them cannot be seen. In this time and space, prisoners place themselves in logical time through the 'time of understanding' in order to become the chosen ones. We always live in logical time. We will argue the point at which Lacan destroys logical time in psychoanalysis. Time in Lacanian psychoanalysis transcends time divisions of the past, present, and future. Our time is always the past in the present. In Lacanian psychoanalysis, logical time is the time in the Other. The transcendence of the Lacanian psychoanalysis concept of time shows the deviation of logical time. In this text, We try to prove how Lacan contrasts psychoanalysis and the problem of time with time in the other. First, we will examine how logical time and impulse are related in psychoanalysis. Second, the postmortemity of the signifient (signifier) will be discussed. Third, Lacan psychoanalysis will present the transcendence of time. In conclusion, We will present the view that the time of Lacan psychoanalysis is flowing backwards. In Lacanian psychoanalysis, we try to prove that logical time is in the territory of the Other and is infinite time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.129-136
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• 2017

Geographic Information System The geographic information system (GIS) has been limited to the government and some public sectors. Recently, the market has been diversified by combining with other areas such as mobile and CRM (Customer Relationship Management). The development direction of GIS technology in the 21st century is Web GIS, 3D GIS, mobile GIS, LBS, etc. as general technology for GIS application system development and spatial information service. In this study, we developed a new concept marking nail (a marking nail with built - in intelligent storage memory device) from the function of simple positioning of a marking nail related to a previously used underground item,, Burial depth, pipe thickness, piping material, management agency, contractor, contact, etc.) and store it in DB server, if necessary.Make it available in the right place. Through this research, it is possible to prevent and minimize various accidents caused by irregular excavation works, etc., and to provide information for establishing countermeasures related to sink holes. In order to provide systematic and reliable information on underground burial management, it was proposed to input information conveniently in the field, and the purpose was to reduce the incidence of buried underground pipes absolutely.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.80-81
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• 2012

Recently, one of the critical issues in the etching processes of the nanoscale devices is to achieve ultra-high aspect ratio contact (UHARC) profile without anomalous behaviors such as sidewall bowing, and twisting profile. To achieve this goal, the fluorocarbon plasmas with major advantage of the sidewall passivation have been used commonly with numerous additives to obtain the ideal etch profiles. However, they still suffer from formidable challenges such as tight limits of sidewall bowing and controlling the randomly distorted features in nanoscale etching profile. Furthermore, the absence of the available plasma simulation tools has made it difficult to develop revolutionary technologies to overcome these process limitations, including novel plasma chemistries, and plasma sources. As an effort to address these issues, we performed a fluorocarbon surface kinetic modeling based on the experimental plasma diagnostic data for silicon dioxide etching process under inductively coupled C4F6/Ar/O2 plasmas. For this work, the SiO2 etch rates were investigated with bulk plasma diagnostics tools such as Langmuir probe, cutoff probe and Quadruple Mass Spectrometer (QMS). The surface chemistries of the etched samples were measured by X-ray Photoelectron Spectrometer. To measure plasma parameters, the self-cleaned RF Langmuir probe was used for polymer deposition environment on the probe tip and double-checked by the cutoff probe which was known to be a precise plasma diagnostic tool for the electron density measurement. In addition, neutral and ion fluxes from bulk plasma were monitored with appearance methods using QMS signal. Based on these experimental data, we proposed a phenomenological, and realistic two-layer surface reaction model of SiO2 etch process under the overlying polymer passivation layer, considering material balance of deposition and etching through steady-state fluorocarbon layer. The predicted surface reaction modeling results showed good agreement with the experimental data. With the above studies of plasma surface reaction, we have developed a 3D topography simulator using the multi-layer level set algorithm and new memory saving technique, which is suitable in 3D UHARC etch simulation. Ballistic transports of neutral and ion species inside feature profile was considered by deterministic and Monte Carlo methods, respectively. In case of ultra-high aspect ratio contact hole etching, it is already well-known that the huge computational burden is required for realistic consideration of these ballistic transports. To address this issue, the related computational codes were efficiently parallelized for GPU (Graphic Processing Unit) computing, so that the total computation time could be improved more than few hundred times compared to the serial version. Finally, the 3D topography simulator was integrated with ballistic transport module and etch reaction model. Realistic etch-profile simulations with consideration of the sidewall polymer passivation layer were demonstrated.

• Journal of Acupuncture Research
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• v.18 no.5
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• pp.122-134
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• 2001

The effects of Cervus elaphus and Cervus elaphus aquapuncuture on body weight, protein efficiency ratio, body length, serum growth hormone and intellectual development were studied for thirty-four days. The results were summarized as follows. 1. Body weight significantly increased in Cervus elaphus aquapuncture oral administration group compared to GH groups. 2. Protein efficiency ratio had no significant difference within all groups. 3. Body length significantly increased in Cervus elaphus aquapuncture group compared to GH injection group on 3rd day, tail length significantly increased in Cervus elaphus aquapuncture group and Cervus elaphus aquapuncture oral administration group compared to GH injection group but, body length has no significant difference within all groups. 4. Serum GH significantly increased in Cervus elaphus aquapuncture oral administration group compared to that of GH injection group. 5. As results of observing memory acquisition using Morris water maze system, there was no significant difference within all groups. 6. As results of observing retention using Morris water maze system, staying times significantly increased in Cervus elaphus aquapuncture oral administration group compared to that of GH injection group at Ist trial and 3rd trial. 7. As results of observing staining intensity of NADPH-d-positive neurons in tissue of hippocampal part, significant increasing of staining intensity were observed in septum and VDB of hippocampus in Cervus elaphus aquapuncture oral administration group compared to that of GH injection group. According to the above results, it is concluded that Cervus elaphus oral administration and Cervus elaphus aquapuncture on acupoint G39 showed effects on growth and intellectual development of animals.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.257-257
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• 2007

고밀도 FeRAM (Ferroe!ectric Random Access Memory) 소자를 개발하기 위해서는 강유전체 물질을 이용한 안정적인 스텍형의 커패시터 개발이 필수적이다. 특히 $(Bi,La)_4Ti_3O_{12}$ (BLT) 강유전체 물질을 이용하는 경우에는 낮은 열처리 온도에서도 균질하고 높은 값의 잔류 분극 값을 확보하는 것이 가장 중요한 과제 중의 하나이다. 불행히도, BLT 물질은 a-축으로는 약 $50\;{\mu}C/cm^2$ 정도의 높은 잔류 분극 값을 갖지만, c-축 방향으로는 $4\;{\mu}C/cm^2$ 정도의 낮은 잔류 분극 값을 나타내는 동의 강한 비등방성 특성을 보인다. 따라서 BLT 박막에서 각각 입자들의 크기 및 결정 방향성을 세밀하게 제어하는 것은 무엇보다 중요하다. 본 연구에서는 16 Mb의 1T/1C (1-transistor/1-capacitor) 형의 FeRAM 소자를 BLT 박막을 적용하여 제작하였다. 솔-젤 (sol-gel) 용액을 이용하여 스핀코팅법으로 BLT 박막을 증착하고, 후속 열처리 공정을 RTP (rapid thermal process) 공정을 이용하여 수행하였다. 커패시터의 하부 전극 및 상부 전극은 각각 Pt/IrOx/lr 및 Pt을 적용하였다. 반응성 이온 에칭 (RIE: reactive ion etching) 공정을 이용하여 커패시터를 형성시킨 후, 32k-array (unit capacitor: $0.68\;{\mu}m$) 패턴에서 측정한 스위칭 분극 (dP=P*-P^) 값은 약 $16\;{\mu}C/cm^2$ 정도이고, 웨이퍼 내에서의 균일도도 2.8% 정도로 매우 우수한 특성을 보였다. 그러나 단위 셀들의 특성을 평가하기 위하여 bit-line의 전압을 측정한 결과, 약 10% 정도의 커패시터에서 불량이 발생하였다. 그리고 이러한 불량 젤들은 매우 불규칙적으로 분포함을 확인할 수 있었다. 이러한 불량 원인을 파악하기 위하여 양호한 젤과 불량이 발생한 셀에서의 BLT 박막의 미세구조를 분석하였다. 양호한 셀의 BLT 박막 입자들은 불량한 셀에 비하여 작고 비교적 균일한 크기를 갖고 있었다. 이에 비하여 불량한 셀에서의 BLT 박막에는 과대 성장한 입자들이 존재하고 이에 따라서 입자 크기가 매우 불균질한 것으로 확인되었다. 또 이러한 과대 성장한 입자들은 거의 모두 c-축 배향성을 나타내었다. 이상의 실험 결과들로부터, BLT 박막을 이용하여 제작한 FeRAM 소자에서 발생하는 불규칙한 셀 불량의 주된 원인은 c-축 배향성을 갖는 과대 성장한 입자의 생성임을 알 수 있었다. 즉 BLT 박막을 이용하여 FeRAM 소자를 제작하는 경우, 균일한 크기의 입자 및 c-축 배향성의 입자 억제가 매우 중요한 기술적 요소임을 알 수 있었다.

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.327-332
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• 2011

Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.

• The Journal of the Convergence on Culture Technology
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• v.8 no.3
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• pp.291-296
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• 2022

This study was conducted on curcumin which had increased bioavailability as a potential AChE inhibitor for the treatment of neurodegenerative diseases. The purpose of this study is to confirm the in vitro neuroprotective effect on Aricumin (turmeric extract). To confirm the neuroprotective effect, AChE inhibition for Aricumin was evaluated, and cell viability was analyzed for HT-22cell, and oxidative stress (glutamate, H₂O₂)-induced HT-22 cytotoxicity was evaluated. As a result of the change in the AChE inhibition rate of Aricumin (Turmeric extract), it was confirmed that Aricumin at a concentration of 39.06㎍/ml or higher inhibited AChE activity by about 20% and more. And it was confirmed that the cytotoxicity of HT-22 cells induced by oxidative stress (Gluamate 5 mM and H₂O₂ 500 µM) was significantly inhibited from 0.01 to 0.1 mg/ml concentration (p<005). These results suggest that Aricumin (turmeric extract) have potential neuroprotective effects.

• Journal of Biosystems Engineering
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• v.7 no.2
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• pp.18-29
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• 1983

A low cost and versatile data acquisition system for the field and laboratory use was developed by using a single board microcomputer. Data acquisition system based on a Z80 microprocessor was built, tested and modified to obtain the present functional system. The microcomputer developed consists of 6 kB ROM, 5 kB RAM, 6-seven segment LED display, 16-Hex. key and 8 command key board. And it interfaces with an 8 channel, 12 bits A/D converter, a microprinter, EPROM programmer for 2716, and RS232C interface to transfer data between the system and HP3000 mini-computer manufactured by Hewlett Packard Co., A software package was also developed, tested, and modified for the system. This package included drivers for the AID converter, LED display, key board, microprinter, EPROM programmer, and RS232c interface. All of these programs were written in 280 assembler language and converted to machine codes using a cross assembler by HP3000 computer to the system during modifying stage by data transferring unit of this system, then the machine language wrote to the EPROM by this EPROM programmer. The results are summarized as follows: 1. Measuring program developed was able to control the measuring intervals, No. of channels used, and No. of data, where the maximum measuring speed was 58.8 microsec. 2. Calibration of the system was performed with triangle wave generated by a function generator. The results of calibration agreed well to the test results. 3. The measured data was able to be written into EPROM, then the EPROM data was compared with original data. It took only 75 sec. for the developed program to write the data of 2 kB the EPROM. 4. For the slow speed measurements, microprinter instead of EPROM programmer proved to be useful. It took about 15 min. for microprinter to write the data of 2 kB. 5. Modified data transferring unit was very effective in communicating between the system and HP3000 computer. The required time for data transferring was only 1~2 min. 6. By using DC/DC converting devices such as 78-series, 79-series. and TL497 IC, this system was modified to convert the only one input power sources to the various powers. The available power sources of the system was DC 7~25 V and 1.8 A.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}