• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.521-524
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• 1990

There is an increasing interest in high-speed signal processing in modern telecommunication and consumer electronics applications. HDTV, ISDN. A limiting factor in Op-Amp based analog integrated circuits is the limited useful frequency range. This research program will develop a new CMOS Op-Amp architecture with improved gainband width product. The new design CMOS Op-Amp will achieve up to 100MHz unity gainband width with a 1.5-micron design rule.

• ETRI Journal
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• v.31 no.2
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• pp.201-208
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• 2009

This paper proposes a spiral-shaped power island structure that can effectively suppress simultaneous switching noise (SSN) when the power plane drives high-speed integrated circuits in a small area. In addition, a new technique is presented which greatly improves the resonance peaks in a stopband by utilizing ${\lambda}$/4 open stubs on a conventional periodic electromagnetic bandgap (EBG) power plane. Both proposed structures are simulated numerically and experimentally verified using commercially available 3D electromagnetic field simulation software. The results demonstrate that they achieve better SSN suppression performance than conventional periodic EBG structures.

• ETRI Journal
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• v.36 no.4
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• pp.617-624
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• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.220-227
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• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

• Journal of the Optical Society of Korea
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• v.20 no.6
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• pp.784-793
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• 2016

We present a single shot low coherence white light Hilbert phase microscopy (WL-HPM) for quantitative phase imaging of Si optoelectronic devices, i.e., Si integrated circuits (Si-ICs) and Si solar cells. White light interferograms were recorded by a color CCD camera and the interferogram is decomposed into the three colors red, green and blue. Spatial carrier frequency of the WL interferogram was increased sufficiently by means of introducing a tilt in the interferometer. Hilbert transform fringe analysis was used to reconstruct the phase map for red, green and blue colors from the single interferogram. 3D step height map of Si-ICs and Si solar cells was reconstructed at multiple wavelengths from a single interferogram. Experimental results were compared with Atomic Force Microscopy and they were found to be close to each other. The present technique is non-contact, full-field and fast for the determination of surface roughness variation and morphological features of the objects at multiple wavelengths.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.105-111
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• 2007

In this paper, we designed and fabricated a 3-dB tandem coupler using air-bridge technology for millimeter-wane monolithic integrated circuits, operating at W-band($75{\sim}110\;GHz$) frequency. Tightly edge-coupled CPW line has low directivity due to different even-mode and odd-mode phase velocity. To overcome this disadvantage, a 3-dB tandem coupler which comprises the two-sectional weakly parallel-coupled lines with equal phase velocity was designed at W-band. The proposed coupler was fabricated using air-bridge technology to monolithically materialize the uniplanar coupler structure instead of conventional multilayer or wire bonded structure. From the measurements, the coupling coefficient of $2.9{\sim}3.6\;dB$ and the good phase difference of $91.2{\pm}2.9^{\circ}$ were obtained in broad frequency range of $75{\sim}100\;GHz$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.