• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.15 no.4
• /
• pp.143-152
• /
• 2016

In this paper, a MMIC double balanced mixer that can be applied to the tele-communication band is designed and LO power optimization for the mixer is discussed. The chip of the MMIC double-balanced mixer is fabricated on GaAs substrate with the size of $4{\times}4mm^2$. Optimization study of LO power for the MMIC double-balanced mixer proposed in this paper is conducted for the Input IP3 (IIP3) regarding on the linearity of the input signal. When LO power level of+16 dBm is applied to the mixer, IIP3 is obtained to be approximately 23.2 dBm, which is the most outstanding characteristic.

• Journal of Korea Society of Industrial Information Systems
• /
• v.6 no.4
• /
• pp.48-53
• /
• 2001

A three-stage low noise amplifier(LNA) for the Base-station of the IMT-2000 is designed and implemented. In the first stage, a GaAs HJt-FET which has good noise characteristics is made use of. Monolithic microwave integrated circuits(MMICS) are used in the second and the third stage to achieve both the high gain and high output power. Although the balanced amplifier is used to reduce the input VSWR, it is done only in the first stage because we have to minimize the noise figure attributed to the phase difference of the balanced amplifier. It is shown that the implemented LNA has the gai over 39.74dB, the gain flatness less than ±0.4dB, the noise figure below 0.97dB, input and output VSWRs less than 1.2, and OIP₃(output third order intercept point) of 38.17dBm in the operating frequency range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.17 no.9 s.112
• /
• pp.811-820
• /
• 2006

Ultra wideband CPW batons are proposed in this paper. The proposed talons are consisted of ultra wideband multi-stage Wilkinson dividers and 'X'-shaped $180^{\circ}$ out-of-phase generator. Bottom-bridges and via-holes are used to connect CPW ground lines instead of the conventional air-bridges which require troublesome manual working in fabrication with HMIC(Hybrid Microwave Integrated Circuits) substrates. The proposed CPW batons have ultra wideband of 3 or $10(=F_{figh}/F_{low})$ theoretically, the wideband characteristics and S-parameters of the basis Wilkinson divider are directly converted to those of the proposed batons. The proposed batons are so compact and small compared to the conventional Wilkinson batons because no additional area for out-of-phase section is required. So the size of the proposed batons is exactly the same as that of the basis Wilkinson dividers. As examples, 3-stage and 7-stage wideband Wilkinson dividers are converted to the proposed batons. Their measured operating bandwidth are $1\sim3GHz$ and $0.8\sim5GHz$, respectively, with excellent matching, isolation and power division performances. The measured magnitude and phase balance errors are ${\pm}0.5dB\;and\;0.45\;dB,\;and\;{\pm}5^{\circ}\;and\;{\pm}10^{\circ}C$ over $1\sim3GHz\;and\;0.8\sim5GHz$, respectively.

• Journal of Satellite, Information and Communications
• /
• v.5 no.2
• /
• pp.82-86
• /
• 2010

In this paper, a power amplifier module for WCDMA base-station applications is designed and implemented using GaN field-effect transistors (FETs), which uses an envelope tracking bias system. The designed module consists of an high gain MMIC amplifier, a driver amplifier, a power amplifier, and bias circuits for envelope tracking applications. Especially, a FET bias sequencing circuit and two isolators are integrated for stable RF operations. All circuits are assembled within a single housing, so its dimension is just $17.8{\times}9.8{\times}2.0\;cm3$. Measured results show that the developed power amplifier module has good envelope tracking capability: the power-added efficiency of 35% at the output power range from 30dBm to 40dBm over a wide range of drain bias.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.9 no.4
• /
• pp.506-514
• /
• 1998

The design and fabrication of X-band(11.7~12 GHz) 2-stage monolithic microwave integrated circuit(MMIC) low noise amplifier (LNA) for active antenna are presented using $0.15{\mu}m\times140{\mu}m$ AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (P-HEMT). In each stage of the LNA, a series feedback by using a source inductor is used for both input matching and good stability. The measurement results are achieved as an input return loss under -17 dB, an output return loss under -15dB, a noise figure of 1.3dB, and a gain of 17 dB at X-band. This results almost concur with a design results except noise figure(NF). The chip size of the MMIC LNA is $1.43\times1.27$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.479-479
• /
• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.14 no.3
• /
• pp.15-20
• /
• 2015

After the US government declared 3D printing technology a next-generation manufacturing technology, there have been many practical studies conducted to expand 3D printing technology to manufacturing technologies, called AMERICA MAKES. In particular, the Keck Center, located at the University of Texas at El Paso, has studied techniques for easily combing the 3D stacking process with space mobility and expanded these techniques to simultaneous staking techniques for multiple materials. Additionally, it developed convergence manufacturing techniques, such as direct inking techniques, in order to produce a module structure that combines electronic circuits and components, such as CUBESET. However, in these studies, it is impossible to develop a unified system using traditional independent through simple sequencing connections. This is because there are many problems in the integration between the stacking modeling of 3D printers and post-machining, such as thermal deformations, the precision accuracy of 3D printers, and independently driven coordinate problems among process systems. Therefore, in this paper, the integration method is suggested, which combines these 3D printers and subsequent machining process systems through an Internet-based cloud. Additionally, the sequential integrated system of a 3D printer, an NC milling machine, machine vision, and direct inking are realized.

• Korean Journal of Materials Research
• /
• v.23 no.10
• /
• pp.550-554
• /
• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.3
• /
• pp.158-164
• /
• 2000

In recent year, desire and request fer micro automation are growing rapidly covering the whole range of the industry. This has been caused mainly by request of more accurate manufacturing process due to a higher density of integrated circuits in semiconductor industry. This paper presents a six d.o.f fine motion stage using magnetic levitation technique, which is one of actuating techniques that have the potential for achieving such a micro motion. There is no limit in motion resolution theoretically that the magnetically levitated part over a fixed stator can realize. In addition, it Is possible to manipulate the position and the force of the moving part at the same time. Then, the magnetic levitation technique is chosen into the actuating method. However, we discuss issues of design, kinematics, dynamics, and control of the proposed system. And a few experimental results fur step input are given.

• Journal of information and communication convergence engineering
• /
• v.13 no.3
• /
• pp.172-179
• /
• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.