• 한국ITS학회 논문지
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• 제15권4호
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• pp.143-152
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• 2016

본 논문에서는 이동통신대역에 사용 가능한 MMIC(Monolithic Microwave Integrated Circuits) 이중평형 주파수 혼합기(Double Balanced Mixer)를 설계하고 LO 전력 최적화에 관한 연구를 다룬다. 본 논문에서 제안한 MMIC 이중평형 주파수 혼합기의 칩 크기는 $4{\times}4$[$mm^2$]이며, GaAs 기판을 사용한다. LO power에 대한 최적화 연구는 입력신호의 선형성에 대한 Input IP3(IIP3)에 대해서 진행하며, LO power+16 dBm을 인가했을 때 IIP3성분이 약 23.2dBm을 보여 가장 우수한 특성을 나타내었다.

• 한국산업정보학회논문지
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• 제6권4호
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• pp.48-53
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• 2001

TMT-2000 기지국용 3단 저잡음 증폭기를 설계하고 제작한다. 첫째 단에서의 증폭소자는 잡음특성이 좋은 GaAs HJ-FET를 사용하고, 둘째 및 셋째 단에는 이득과 출력전압이 높은 값을 갖도록 하기 위해 모노리딕(monolithic) 마이크로웨이브 집적회로를 사용한다. 또한 입력 정재파비를 낮추기 위해서 평형증폭기를 사용하는데, 이 평형증폭기의 위상차로 인한 잡음지수를 최소화하기 위해서 첫째 단에만 제한적으로 사용한다. 제작된 증폭기는 동작 주파수에서 이득 39.74$\pm$0.4dB, 최대잡음지수 0.97dB, 입.출력 정재파비 1.2 이하 및 OIP$_3$ 특성은 38.17dBm을 나타낸다.

• 한국전자파학회논문지
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• 제17권9호
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• pp.811-820
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• 2006

본 논문에서는 초광대역 CPW(Coplanar Waveguide) 발룬을 제안한다. 제 안된 발룬에는 초광대역을 위한 다단윌킨슨 전력 분배기 구조와 CPW의 "X"-형태의 $180^{\circ}$의 위상차 생성 구조를 갖는다. 또한 CPW 선로에 필요한 접지간 연결을 위하여 bottom-bridge와 via-hole을 사용하는 방법을 제안하여 HMIC(Hybrid Microwave Integrated Circuits) 제작 공정에서 CPW 회로 제작을 편리하게 하였다. 제안된 발룬은 이론적으로 3 또는 10의 초광대역 주파수 대역폭$(=F_{high}/F_{low})$을 갖는데, 윌킨슨 분배기의 초광대역 주파수 특성 과 S-파라미터 특성을 그대로 발룬의 특성으로 전환된다. 제안된 발룬은 $180^{\circ}$ 위상차 생성을 위한 별도의 추가적인 면적을 요구하지 않으므로, 설계의 바탕이 되는 전력 분배기와 같은 크기를 갖는다. 예로써 제작한 3단과 7단 분배기 구조의 발룬은 각각 $1\sim3GHz,\;0.8\sim5GHz$의 주파수 대역에서 우수한 정합 특성, 출력 단자+간 격리 특성, ${\pm}0.5dB$과 ${\pm}0.45dB$의 전력분배 비 에러를 보여주고 있다. 또한 출력 단자간 위상차 에러는 각각 ${\pm}5^{\circ}$와 ${\pm}10^{\circ}$이다.

• 한국위성정보통신학회논문지
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• 제5권2호
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• pp.82-86
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• 2010

본 논문에서는 포락선추적 기능을 갖는 WCDMA 기지국에 사용될 수 있는 GaN FET를 이용한 전력증폭기 모듈을 설계하고, 제작 및 측정결과를 제시하였다. 개발된 전력증폭기 모듈은 소신호 RF 신호를 입력받아 고이득 MMIC 증폭기, 구동 증폭기 및 전력 증폭기 등을 거쳐 10W 이상의 출력을 생성할 수 있다. 또한, Envelope Tracking 응용을 위해서 최종 전력증폭기의 Drain 전압이 가변되어도 전체 모듈이 안정적으로 동작할 수 있도록 발진방지회로, Isolator, 음전압 우선인가 바이어스 회로가 설계되었다. 모든 바이어스 회로와 RF회로를 $17.8{\times}9.8{\times}2.0\;cm3$ 크기의 하우징 안에 집적화하여 소형화시켰다. 측정결과 바이어스 전압이 4V에서 28V까지 가변할 경우 30dBm에서 40dBm까지 출력이 가변되면서도 35%이상의 일정한 효율 특성을 나타내어 포락선 추적 기능을 수행할 수 있음을 확인하였다.

• 한국전자파학회논문지
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• 제9권4호
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• pp.506-514
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• 1998

능동 안테나용 X-band(11.7~12 GHz)단일 칩 초고주파 집적회로(Monolithic Microwave Integrated Circuits, MMICs) 저잡음 증폭기(Low Noise Amplifier, LNA)를 $0.15{\mu}m\times140{\mu}m$ AlGaAs/InGaAs/GaAs 고속 전자 이동도 트랜지스터(Pseudomorphic-High Electron Mobility Transistor, P-HEMT)를 이용하여 2단으로 설계하고 제작하였다. 증폭기의 안정도 특성을 위해 이득이 다소 감소하나 입력정합이 쉽고 안정도가 좋은 소스 인턱터를 사용하여 저잡음증폭기를 설계하였다. 동작 주파수에서 약 17dB의 이득, 1.3 dB의 잡음 지수 그리고 입.출력 반사손실은 -17~-15dB를 측정 결과로서 얻었다. 이러한 측정 결과는 잡음 지수를 제외하고는 설계 결과와 거의 일치하며, 제작된 MMIC LNA의 칩 크기는 $1.43\tiems1.27mm^2$이다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• 한국기계가공학회지
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• 제14권3호
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• pp.15-20
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• 2015

After the US government declared 3D printing technology a next-generation manufacturing technology, there have been many practical studies conducted to expand 3D printing technology to manufacturing technologies, called AMERICA MAKES. In particular, the Keck Center, located at the University of Texas at El Paso, has studied techniques for easily combing the 3D stacking process with space mobility and expanded these techniques to simultaneous staking techniques for multiple materials. Additionally, it developed convergence manufacturing techniques, such as direct inking techniques, in order to produce a module structure that combines electronic circuits and components, such as CUBESET. However, in these studies, it is impossible to develop a unified system using traditional independent through simple sequencing connections. This is because there are many problems in the integration between the stacking modeling of 3D printers and post-machining, such as thermal deformations, the precision accuracy of 3D printers, and independently driven coordinate problems among process systems. Therefore, in this paper, the integration method is suggested, which combines these 3D printers and subsequent machining process systems through an Internet-based cloud. Additionally, the sequential integrated system of a 3D printer, an NC milling machine, machine vision, and direct inking are realized.

• 한국재료학회지
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• 제23권10호
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• 한국정밀공학회지
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• 제17권3호
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• pp.158-164
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• 2000

In recent year, desire and request fer micro automation are growing rapidly covering the whole range of the industry. This has been caused mainly by request of more accurate manufacturing process due to a higher density of integrated circuits in semiconductor industry. This paper presents a six d.o.f fine motion stage using magnetic levitation technique, which is one of actuating techniques that have the potential for achieving such a micro motion. There is no limit in motion resolution theoretically that the magnetically levitated part over a fixed stator can realize. In addition, it Is possible to manipulate the position and the force of the moving part at the same time. Then, the magnetic levitation technique is chosen into the actuating method. However, we discuss issues of design, kinematics, dynamics, and control of the proposed system. And a few experimental results fur step input are given.

• Journal of information and communication convergence engineering
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• 제13권3호
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• pp.172-179
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• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.