• 한국정보통신학회논문지
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• 제8권3호
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• pp.686-693
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• 2004

WCDMA용 SAW 필터를 제작하기 위하여 mathematica package를 이용한 모의 실험기를 개발하였으며, 전극재료로는 Al-Cu를 사용하였다. 모의실험한 자료를 바탕으로 전극에서 발생하는 ultimate rejection을 줄이기 위해 SFIT형태의 필터를 설계 및 제작하였다. 회절에 의한 현상을 최소화하기 위해 필터의 입력단은 block weighted IDT 형태로, 출력단은 withdrawal weighted IDT형태로 구성하였다. Langasite 기판위에 형성시킨 입 출력 빗살무늬 변환기 전극 수는 50쌍, 두께와 폭은 5000$\AA$와 1λ4(((equation omitted) 3.6$\mu\textrm{m}$)로 하였으며, IDT 전극 폭과 전극간격 은 각각 1λ/16와 1λ/8로 하였다. 제작한 SAW 필터의 특성은 중심주파수는 190MHz, 통과대역은 4MHz이며 저지대역은 -60dB이하로 측정되었다.

• Nuclear Engineering and Technology
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• 제52권7호
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• pp.1557-1564
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• 2020

In this paper, 3D model-based interactive gamma ray shielding package (MIGSHIELD) is developed in virtual reality platform for windows operating system. In MIGSHIELD, the computational methodology is based on point kernel algorithm (PK), several key parameters of PK are obtained using new technique and new methods. MIGSHIELD has interactive capability with virtual world. The main features made in the MIGSHIELD are (i) handling of physical information from virtual world, (ii) handling of arbitrary shapes radioactive source, (iii) calculating the mean free path of gamma ray, (iv) providing interactive function between PK and virtual world, (v) making better use of PK for virtual simulation, (vi) plug and play. The developed package will be of immense use for calculations involving radiation dose assessment in nuclear safety and contributing to fast radiation simulation for virtual nuclear facilities.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1034-1046
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• 2013

본 논문에서는 임의의 고조파 임피던스를 갖는 출력 정합 회로를 이용한 GaN HEMT 전력증폭기의 설계를 보였다. 선정된 GaN HEMT 소자는 TriQuint사의 TGF2023-02이며, 전력증폭기 구성을 위하여 상용 패키지에 패키징하였다. 패키지 입 출력 기준면에서 로드-풀 시뮬레이션을 수행하였다. 기본파에서는 최대 출력, 2차 및 3차 고조파에서는 최대 효율을 갖는 최적 임피던스를 도출하였다. 도출된 임피던스는 fixture에 의하여 임의의 고조파 임피던스를 보였으며, 이를 정합하기 위하여 4개의 전송선으로 구성된 출력 정합 회로를 제안하였다. 최적 임피던스를 정합하기 위한 전송선의 특성 임피던스와 전기각을 수학적으로 도출하였다. 제안된 출력 정합회로를 PCB상에 구현하여 전력증폭기를 제작하였다. 제작된 전력증폭기는 $54.6{\times}40mm^2$의 크기를 가지며, 2.5 GHz에서 8 W 이상의 출력을 보이고, 8 W 출력에서 효율 55 % 이상, 그리고 2차 및 3차 고조파는 모두 35 dBc 이상의 특성을 보였다.

• 한국축산식품학회지
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• 제18권2호
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• pp.115-124
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• 1998

This study was carried out investigate hygienic conditions of domestic packing plant for export and the shelf-life by Japanese standards. vacuum packaged chilled port loins provided by five packers(A, B, C, D and E) were transported to Japan in the same condition, Four packers(A, B, C adn d) produced the samples as hygienic as possible and one packer produced loins in the traditional hygienic condition, In TTC(2,3,5-triphenyl tetrazolium chloride) test all samples showed the negative reaction from the date of the quarantine(14 days after slaughtering) to 50 days The numbers of total plate count(TPC) of A, B, C and D packers that were below 108CFU/g until 50 days were accepted by Japanese Standards but TPC of E packer was over 107CFU/g at 30 days. VBN values increased sig-nificantly(P<0.01) in samples of A,B and D packers in the samples of C packer and E packer at 5% and 0.1% level respectively. The pH values of the vacuum packaged chilled pork for export at 14 days after slaughtering were 5.43∼6.00 In sensory evaluation, A, B, C and D packers which improved hygi-enic condition produced the products with good color and appearance. low drip until 40 days storage at $0^{\circ}C$ But as the storage time increase off-flavor occured at 40days in A and D packer and at 50days in B and C packer. In conclusion according to the above results of microbiological physicochemical and sensory evalution the edible periods of Korean vacuum package chilled porks may be estimated to 40∼50 days for the packers who improved hygienic condition and the shelf lives were calculated as 32∼40 days from edible period by a factor of 0.8(safety coefficient) while that of the pork from E packer which was produced in the traditional hygienic condition was estimated to 30 days after slaughtering at $0^{\circ}C$ Therefore the shelf-life of the pork of E packer would be only 24 days.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 D
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• pp.2109-2110
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• 2006

유한요소법은 전자기, 기계, 또는 다른 공학 분야에서 다루는 풀기 어려운 복잡한 문제들을 해석하는데 널리 사용되고 있는 수치해석기법이다. CEMTool은 MATLAB과 유사한 과학기술 범용 패키지로서, 간편한 명령어 방식의 문법과 블록 다이어그램 설계, 이공학 전반의 함수 등의 다양한 기능들을 제공한다. 본 논문에서는 범용 공학 소프트웨어인 CEMTool 환경에서 실행되는 GUI 3D FEM 패키지에 대해 기술한다. FEM 해석의 일반적 단계인 전처리, 솔버, 후처리 단계별로 나누어 각 단계의 구조와 특징 등을 기존의 CEMTool 2D FEM 패키지, MATLAB PDE Toolbox, FEMLAB2.2와 비교하여 자세히 살펴보기로 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1366-1367
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• 2006

Embedded capacitor technology is one of the effective packaging technologies for further miniaturization and higher performance of electric package systems. So we used the 3D EM simulator for embedded capacitor design in 8-layed PCB(Printed Circuit Board). The designed capacitors value are 2 pF, 5pF, 10 pF, respectly. we investigated characteristics of capacitance - frequency and SRF(Self Resonance Frequency) as changing the rate of hight and width of upper pad of embedded capacitors.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.595-596
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• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• 설비공학논문집
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• 제15권8호
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• pp.697-703
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• 2003

Cogeneration is the simultaneous generation of heat and electricity in a single unit, and is a highly energy-efficient technology compared to the independent generation of both products. Therefore, cogeneration has been widely introduced in many countries for use in industrial, commercial and residential applications. However, there have been few models with an output of less than 100 kilowatt. In the present study, a spark ignited gas engine with electric generation output of 10 kilowatts was developed for micro cogeneration package. The gas engine shows 26.7% of electric generation efficiency, NOx emission less than 10 ppm at 13% oxygen, 82 dB of Noise level, and about 3 seconds of switching time from idling to nominal power.