• Title/Summary/Keyword: 3D Graphics accelerator

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A Design of a Mobile Graphics Accelerator based on OpenVG 1.0 API

  • Kwak, Jae-Chang;Lee, Kwang-Yeob
    • Journal of information and communication convergence engineering
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    • v.6 no.3
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    • pp.289-293
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    • 2008
  • In this paper, we propose the hardware architecture to accelerate 2D Vector graphics process for mobile devices. we propose the Transformation Unit Architecture that considerates the operation dependency. It has 3 cycles excution time and uses 2 multipliers and 2 adders. Proposed paint generation unit uses a LUT method, so it does not execute color interpolation which needs to be calculated every time. The proposed OpenVG 1.0 Accelerator achieved a 2.85 times faster performance in a tiger model.

An efficient pipelined architecture for 3D graphics accelerator (3차원 그래픽 가속기의 효율적인 파이프라인 설계)

  • 우현재;정종철;이문기
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.357-360
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    • 2002
  • This paper is proposed about an efficient pipelined architecture for 3D graphics accelerator to reduce Cache miss ratio. Because cache miss takes a considerable time, about 20∼30 cycle, we reduce cache miss ratio to use pre-fetch. As a result of simulation, we figure out that the miss ratio of cache depends on the size of tile, cache memory and auxiliary cache memory. We can save 6.6% cache miss ratio maximumly.

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A design of low power structures of texture caches for mobile 3D graphics accelerator (모바일 3D 그래픽 가속기를 위한 저전력 텍스쳐 캐쉬 구조 설계)

  • Kim, Young-Sik;Lee, Jae-Young
    • Journal of Korea Game Society
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    • v.6 no.4
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    • pp.63-70
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    • 2006
  • This paper studied various low power structures of texture caches for mobile 3D graphics accelerator to reduce the memory latency of texture data. Also the paper designed the texture cache with the variable threshold values of power mode transition according to the filtering algorithms. In the trace driven simulation, we compared the performance of those structures using Quake game engine as the benchmark. Also the algorithm was proposed and verified by the simulation, which has variable threshold values of power mode transitions according to the selected texture filtering method.

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A Study on the 3 Dimension Graphics Accelerator for Phong Shading Algorithm (Phong Shading 알고리즘을 적용한 3차원 영상을 위한 고속 그래픽스 가속기 연구)

  • Park, Youn-Ok;Park, Jong-Won
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.5
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    • pp.97-103
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    • 2010
  • There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

Power Estimation of The Embedded 3D Graphics Renderer (내장형 3차원 그래픽 렌더링 처리기의 전력소모)

  • Jang, Tae-Hong;Lee, Moon-Key
    • Journal of Korea Game Society
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    • v.4 no.3
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    • pp.65-70
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    • 2004
  • The conventional 3D graphic accelerator is mainly focused on high performance in the application area of computer graphic and 3D video game How ever the existing 3D architecture is not suitable for portable devices because of its huge power. So, we analyze the embedded 3D graphics renderer. After the analyzing, to reduce the power, triangle set-up stage and edge walking stage are executed sequentially while scan-line processing stage and span processing stage which control performance of 3D graphic accelerator are executed parallel.

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A Design of a 8-Thread Graphics Processor Unit with Variable-Length Instructions

  • Lee, Kwang-Yeob;Kwak, Jae-Chang
    • Journal of information and communication convergence engineering
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    • v.6 no.3
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    • pp.285-288
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    • 2008
  • Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

Implementation of a 3D Graphics Hardwired T&L Accelerator based on a SoC Platform for a Mobile System (SoC 플랫폼 기반 모바일용 3차원 그래픽 Hardwired T&L Accelerator 구현)

  • Lee, Kwang-Yeob;Koo, Yong-Seo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.59-70
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    • 2007
  • In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

A Design of 3D Graphics Geometry Processor for Mobile Applications (휴대 단말기용 3D Graphics Geometry Processor 설계)

  • Lee, Ma-Eum;Kim, Ki-Chul
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.917-920
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    • 2005
  • This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

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Design of Pipelined Floating-Point Arithmetic Unit for Mobile 3D Graphics Applications

  • Choi, Byeong-Yoon;Ha, Chang-Soo;Lee, Jong-Hyoung;Salclc, Zoran;Lee, Duck-Myung
    • Journal of Korea Multimedia Society
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    • v.11 no.6
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    • pp.816-827
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    • 2008
  • In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

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A Low Power 3D Graphics Accelerator Considering Both Active and Standby Modes for Mobile Devices (모바일기기의 동작모드와 대기모드를 모두 고려한 저전력 3차원 그래픽 가속기)

  • Kim, Young-Sik
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.2
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    • pp.57-64
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    • 2007
  • This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.