• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.119-128
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• 2008

In this paper, we propose a developing approach of 600 W super high frequency(SHF) traveling wave tube amplifier (TWTA) for communications. Also, we make a TWTA called the experimental-TWTA(ETWTA), which uses a cathode ripple reduction technique to improve RF performance. After implementation, we discuss, and compare it with some other TWTAs. Its RF performance is better than that of other TWTAs. Therefore, this methodology can be used to develop the high power SHF TWTA for communications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.4
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• pp.307-313
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• 2019

The traveling wave tube amplifier (TWTA), which can be applied to the Ka-band millimeter-wave multi-mode seeker, consists of an high voltage power supply(HVPS), a grid modulator, a command and control, and an RF assembly. We designed a power supply that generates a -17.9 kV high voltage by synchronizing the pulse repetition frequency(PRF) and power supply switching frequency(i.e. synchronization frequency), and a high-speed grid-switching modulator for RF pulse modulation. The TWTA, which is fabricated through miniaturization with a volume of 3.18 L, has high pulse switching characteristics of up to 18.5 ns. The maximum rise/fall time of the grid on/bias signal and peak power is more than 564.9 W. Moreover, an excellent spurious performance of -68.4 dBc or less was confirmed within the range of PRF and PRF/2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

• Current Optics and Photonics
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• v.5 no.2
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• pp.186-190
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• 2021

In this study, a compact, picosecond, mid-infrared 3.8 ㎛ MgO:PPLN optical parametric oscillator (OPO) laser output with high peak power is realized using a master oscillator power amplifier (MOPA) 1 ㎛ solid-state laser seeded by a picosecond fiber laser as the pump source. The pump source was a 50 MHz and 10 ps fiber seed source. After AOM pulse selection and two-stage solid-state amplification, a 1,064 nm laser output with a repetition frequency of 1-2 MHz, pulse width of 9.5 ps, and a maximum average power of 20 W was achieved. Furthermore, a compact short cavity with a unsynchronized pump is adopted through the design of an OPO cavity structure. When the injection pump power was 15 W and the repetition frequency was 1 MHz, the average output power of idler light was 1.19 W, and the corresponding peak power was 119 kW. The optical conversion efficiency was 7.93%. When the repetition frequency was increased to 2 MHz, the average output power of idler light was 1.63 W, the corresponding peak power was 81.5 kW, and the optical conversion efficiency was 10.87%. At the same time, the output wavelength was measured at 3,806 nm, and the beam quality was MX2 = 3.21 and MY2 = 3.34.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.52-59
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• 2010

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.601-605
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• 2004

A new high efficiency and low profile on-board DC/DC converter for digital car audio amplifier is proposed. The proposed converter shows the continuous input current, no DC excitation current of the transformer, the minimized electro-magnetic interference (EMI), no output inductor, and the low voltage stress of the secondary rectifier diodes. The 60W industrial sample of the proposed converter is implemented for digital car audio amplifier and the measured efficiency is $88.3\%$ at nominal input voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.