• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.340-343
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• 1990

Recently, Power Electronics system increase makes harmonics and low input power factor problem. In this paper present new analysis method of PWM Boost AC/DC Converter. This PWM AC/DC Converter is capability of unity power factor, control of DC side voltage level, generation, and near sinusoidal current in 3-phase line. The control of this type of converter is widely discussed. And this paper propose new phase convert function and analysis in steady state of system to obtain amplitude and phaser of switching function. This switching function is general solution and it can use in high power approach. And this control method show the clear meaning of control variable. This paper propose new analysis method of Boost AC/DC Converter of steady state and 3-phase 2KW experimental system show its validity.

• Journal of Power Electronics
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• v.10 no.3
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• pp.251-261
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• 2010

The general function of a multilevel converter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new topology is recommended in [1], which benefits from a series connection of sub-multilevel converters. In the procedure described in this reference, despite all the advantages, it is not possible to produce all the steps (odd and even) in the output. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for this topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation and experimental results for a 49-level converter with a maximum output voltage of 200V are presented.

• Journal of Power Electronics
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• v.14 no.3
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• pp.531-540
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• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.1
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• pp.72-83
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• 2013

The paper proposes a new multilevel variable output voltage AC/DC Converter for power supply of power amplifiers used in underwater acoustic sensors. The proposed multilevel variable output voltage AC/DC Converter is composed of two parts. One as the input section is the high efficiency phase-shifted PWM full bridge DC-DC converter to get multiport power sources. The other as the output section is composed of two flying-capacitor 3-level DC-DC converters and a diode bridge circuit to get fast-response and multilevel variable output voltage for an envelope amplifier. Also the paper suggests the detailed circuit topology and design guideline of multilevel variable output voltage AC/DC converter. It also proposes the power balanced control method between 3-level converters and the voltage balanced algorithm for flying capacitors. Its characteristics should be verified by the detailed simulation results. It is anticipated that the proposed converter will be used very well for power amplifiers used in underwater acoustic sensors.

• Journal of the Korean Society for Railway
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• v.19 no.5
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• pp.617-628
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• 2016

This paper proposes the structure of a smart transformer to improve the performance of the 60Hz main power transformer for rolling stock. The proposed smart transformer is a kind of solid state transformer that consists of semiconductor switching devices and high frequency transformers. This smart transformer would have smaller size than the conventional 60Hz main transformer for rolling stock, making it possible to operate AC electrified track efficiently by power factor control. The proposed structure employs a cascade H-Bridge converter to interface with the high voltage AC single phase grid as the rectifier part. Each H-Bridge converter in the rectifier part is connected by a Dual-Active-Bridge (DAB) converter to generate an isolated low voltage DC output source of the system. Because the AC voltage in the train system is a kind of medium voltage, the number of the modules would be several tens. To control the entire smart transformer, the inner DC voltage of the modules, the AC input current, and the output DC voltage must be controlled instantaneously. In this paper, a control algorithm to operate the proposed structure is suggested and confirmed through computer simulation.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.359-360
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• 2017

This paper presents comparison of simulation and experiment in thermal analysis of 3-level PFC. Thermal analysis is necessary to optimize the power conversion system to get higher efficiency. Accordingly, analysis via simulation tools and analytic methods is performed to predict the power losses of converter. Consequently, thermal results of 3-level PFC experiment is compared with thermal analysis.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.5
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• pp.434-441
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• 2016

This paper deals with transformer turns ratio design with the consideration of loss minimization in isolated bidirectional DC-DC converter. Generally, the rms value of current, magnitude of current at switching instance, and duty ratio of a converter vary according to the turns ratio of an isolation transformer in the converter under the same voltages and output power level. Therefore, the transformer turns ratio has an effect on the total loss in a converter. The switching and conduction losses of IGBTs and MOSFETs consisting of dual-active bridge converter are analyzed, and iron and copper losses in an isolation transformer and inductor are calculated. Total losses are calculated and measured in cases of four different transformer turns ratios through simulation and experiment with 3-kW converter, and an optimum turns ratio that provides minimum losses is found. The usefulness of the proposed transformer turns ratio design approach is verified through simulation and experimental results.