• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.5
• /
• pp.16-23
• /
• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.3
• /
• pp.1075-1080
• /
• 2015

A hybrid electric vehicle (HEV) powertrain has more than one energy source including a high-voltage electric battery. However, for a high voltage electric battery, the average current is relatively low for a given power level. Introduced to increase the voltage of a HEV battery, a compact, high-efficiency boost converter, sometimes called a step-up converter, is a dc-dc converter with an output voltage greater than its input voltage. The inductor occupies more than 30% of the total converter volume making it difficult to get high power density. The inductor should have the characteristics of good thermal stability, low weight, low losses and low EMI. In this paper, Mega Flux^® was selected as the core material among potential core candidates. Different structured inductors with Mega Flux^® were fabricated to compare the performance between the conventional air cooled and proposed potting structure. The proposed inductor has reduced the weight by 75% from 8.8kg to 2.18kg and the power density was increased from 15.6W/cc to 56.4W/cc compared with conventional inductor. To optimize the performance of proposed inductor, the potting materials with various thermal conductivities were investigated. Silicone with alumina was chosen as potting materials due to the high thermo-stable properties. The proposed inductors used potting material with thermal conductivities of 0.7W/m·K, 1.0W/m·K and 1.6W/m·K to analyze the thermal performance. Simulations of the proposed inductor were fulfilled in terms of magnetic flux saturation, leakage flux and temperature rise. The temperature rise and power efficiency were measured with the 40kW boost converter. Experimental results show that the proposed inductor reached the temperature saturation of 107℃ in 20 minutes. On the other hand, the temperature of conventional inductor rose by 138℃ without saturation. And the effect of thermal conductivity was verified as the highest thermal conductivity of potting materials leads to the lowest temperature saturations.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.6
• /
• pp.514-521
• /
• 2009

This paper deals with a new overvoltage snubber for a diode-clamped 3-level IGBT inverter. Usually most power converters use snubber circuits to protect the switching devices from voltage spike. However, it is difficult for the diode-clamped multi-level converter to be protected from voltage spike with overvoltage snubber since the series connection of the switching devices. To solve the problem the characteristic of a overvoltage snubber for a DC-DC converter is analyzed, and a new snubber for a diode clamped 3-level inverter is proposed. The performance of the proposed snubber is verified through experiments.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.3
• /
• pp.201-210
• /
• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.2 no.3
• /
• pp.26-36
• /
• 1997

An single stage AC/DC converter based on half bridge topology suitable for low power level applications is proposed. The proposed converter has high power factor, low harmonic distortion, and tight output regulations. Asymmetrical control and synchronous rectification are adopted to reduce the switching loss and rectification loss, respectively. The modelling employing average modelling method and detailed analysis are performed to derive the design equations. According to these design equations, a prototype converter has been designed and experimented. This prototype meets the IEC 555-2 regulations with near unity power factor and high efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1283-1290
• /
• 2003

Recently, PWM Buck AC-AC Converter is widely employed in various industrial applications such as voltage and power regulator, electronic transformer, phase shifter and so on. This paper presents static and dynamic modeling and complete characteristic analysis of a PWM Buck AC-AC converter. Firstly, the three phase converter system is modelled by using DQ transformation whereby we can obtain basic characteristic equations such as voltage gain and power factor as well as state equation and transfer function for control. Secondly, based on the analysis, the feedforward-feedback control technique is also proposed to obtain instantaneous duty level change whereby very fast dynamic response is achieved. Finally, the experimental results show the validity of the modeling, analysis and control.

• Journal of Power Electronics
• /
• v.14 no.3
• /
• pp.507-518
• /
• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• Journal of Power Electronics
• /
• v.17 no.3
• /
• pp.641-652
• /
• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• Proceedings of the KIPE Conference
• /
• 2018.11a
• /
• pp.86-88
• /
• 2018

The three level(3L) neutral point clamped (NPC) voltage source converter (VSC) topology is widely used for grid interface in high power wind energy due to its superior performance as compared to the two level(2L) VS. However, one of the major drawbacks of this topology is the unequal dispersion of loss and therefore the junction temperature among the power devices. The 3L ANPC topology derived from the NPC topology was proposed to resolve this drawback of unequal loss profile of 3L NPC. The 3L ANPC can work under various switching strategies. In this paper a comparative study of the various switching strategies of 3L ANPC using the recently developed 10kV IGCTs which has the capability to raise the current and voltage rating of the wind turbines is carried out. The comparison is performed using ABB make 10kV IGCT 5SHY17L9000 and PLECs simulations.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.300-311
• /
• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.