• Title/Summary/Keyword: 2nd harmonic

Search Result 168, Processing Time 0.024 seconds

Design and Fabrication of the Frequency Multiplier for S-band Transponder (S-대역 트랜스폰더용 주파수 체배기 설계 및 제작)

  • Kim, Byung-Soo;Ko, Bong-Jin
    • Journal of Advanced Navigation Technology
    • /
    • v.10 no.4
    • /
    • pp.348-355
    • /
    • 2006
  • In this paper, frequency multipliers used S-band transponder of the KOMPSAT 3 are designed and fabricated. In the transponder, 108 times multiplier which generate 1st LO signal(2008.8MHz) is comprised of the X9 frequency multiplier, 1st X2 multiplier, 2nd X2 multiplier and the last stage of the X3 frequency multiplier. As results, output power of 8.17 dBm at 2008.8MHz, the harmonic suppression of -56.67dBc, the bandwidth of 14MHz were measured.

  • PDF

Output Characteristics of a Pulsed Ti:sapphire Laser Oscillator Pumped Longitudinally by Second Harmonic Wave of Nd:YAG Laser and a Ti:sapphire Laser Amplifier Operated along the Single Path of the Oscillator Beam (Nd:YAG 레이저의 제 2조화파로 종여기하는 펄스형 Ti:sapphire 레이저 발진기와 이를 이용한 단일경로 형태의 Ti:sapphire 증폭기의 출력특성)

  • Kim, Kyung-Nam;Jo, Jae-Heung;Lim, Gwon;Cha, Byung-Heon
    • Korean Journal of Optics and Photonics
    • /
    • v.18 no.1
    • /
    • pp.66-73
    • /
    • 2007
  • The various output characteristics of a pulsed Ti:sapphire laser oscillator with a plane-parallel resonator, pumped longitudinally by the second harmonic wave of a Nd:YAG laser, and the output of a Ti:sapphire laser amplifier operated along the single path of the oscillator beam were investigated and analyzed. In the case of the oscillator, we measured the spectrum, the pulse buildup time, the temporal duration time of the pulse, and the output energy according to the variation of the pumping energy, resonator length, and the reflectance of the output coupler. And, in the case of the amplifier, we investigated and analyzed the output energy of the amplifier as a function of the time difference between the two pump beams of the oscillator and the amplifier, the pumping energy of the oscillator, and the pumping energy of the amplifier When pump energies of both the oscillator and the amplifier were 18 mJ/pulse, we could find that the output energy of the amplifier increased linearly and gradually up to the time difference of 35 ns. Finally, we determined that the slope efficiencies of the oscillator and the amplifier were 23.5 % and 11.6 %, respectively.

Design and Analysis of Linear Channel-Selection Filter for Direct Conversion Receiver

  • Jin, Sang-Su;Ryu, Seong-Han;Kim, Hui-Jung;Kim, Bum-Man;Lee, Jong-Ryul
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.4 no.4
    • /
    • pp.293-299
    • /
    • 2004
  • An active RC 2nd order Butterworth filter suitable for a baseband channel-selection filter of a direct conversion receiver is presented. The linearity of the 2nd order Butterworth filter is analyzed. In order to improve the linearity of the filter, the operational amplifiers should have a high linear gain and low 3rd harmonic, and the filter should be designed to have large feedback factor. This second order Butterworth filter achieves-14dBV in-channel (400kHz, 500kHz) IIP3, +29dBV out-channel (10MHz, 20.2MHz) IIP3 and 15.6 $nV/\sqrt{Hz}$ input-referred noise and dissipates 10.8mW from a 2.7-V supply. The analysis and experimental results are in good agreement

A Study on Development of the Tidal Database for the Philippines (필리핀을 위한 조석 데이터베이스 개발에 관한 연구)

  • PARK, Eung-Hyun;AHN, Se-Jin;SHIM, Moon-Bo;JEON, Hae-Yeon;KANG, Ho-Yun;KIM, Dae-Hyun
    • Journal of the Korean Association of Geographic Information Studies
    • /
    • v.22 no.4
    • /
    • pp.158-168
    • /
    • 2019
  • Korea Hydrographic and Oceanographic Agency(KHOA) carried out a research project named 'Marine Fisheries Infrastructure Construction and Technology Training for the Philippines' as part of the 1st Official Development Assistance(ODA) from 2015 to 2018. It is preparing for the 2nd ODA project which will begin in 2020. Besides, recently, the Philippines is paying attention to marine territory management and response capability due to problems such as the sea-level rise and coastal erosion caused by climate change. Therefore, before 2nd ODA to the Philippines, this study analyzed the vertical ocean model on the vertical datum in Korea and suggests the direction of development of the vertical ocean modeling system for the vertical datum in the Philippines using the observed data from the permanent tide station which was built by the Philippines ODA research project over the last four years. Moreover, as a pilot study, the Sulu Sea in the Philippines was selected and analyzed by harmonic analysis method. At each tide station, constants for correction had been computed. And the grid-based tidal model was constructed based on this study. As a result of the study, similar tidal characteristic were observed when the prediction and the measured tide were compared by applying the constants for correction between two station in the sea area with similar tidal level. These results could be used as basic data for the 2nd ODA to the Philippines, and contributed to construct and maintain a close cooperation and friendship between Korea and the Philippines.

A Study on Design and Fabrication on X-Band Oscillator for radar system (레이더 시스템용 X-Band 발진기의 설계 및 제작에 관한 연구)

  • 손병문;강중순
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.5 no.7
    • /
    • pp.1210-1218
    • /
    • 2001
  • In this paper, A X-band voltage-controlled hair-pin resonator oscillator(VCHRO) is able to a local oscillator or a signal source in transmitter/receiver of a microwave communication system for mobile radar, is designed and fabricated In order to apply mobile radar system is used the hair-pin resonator stronger on shock or vibration than the dielectric resonator, and also, in order to improvement the phase noise and output power is used a system of serial feedback format A hair-pin resonator was simulated by momentum method of HP ADS and then a oscillator circuit was designed that operates at 10.525 GHz by nonlinear method in harmonic balance simulation. The HRO generated output power of 6.93 dBm at 10.525 GHz, phase noise of -57.74 dBc at 100 kHz offset from carrier and the 2'nd harmonic was suppressed -23.90 dBc.

  • PDF

Design Issues of CMOS VCO for RF Transceivers

  • Ryu, Seong-Han
    • Journal of electromagnetic engineering and science
    • /
    • v.9 no.1
    • /
    • pp.25-31
    • /
    • 2009
  • This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.

Prediction Method of Loudspeaker Driver Characteristics (스피커 드라이브 특성 예측 기법)

  • Park, Soon-Jong;Rho, Sung-Tak
    • The Journal of the Acoustical Society of Korea
    • /
    • v.27 no.7
    • /
    • pp.325-332
    • /
    • 2008
  • The prediction method of TS parameters, frequency response, and electrical input impedance is proposed with physical properties of parts and results of electromagnetic FEA(Finite Element Analysis) in a loudspeaker driver design. In design for weight reduction and improvement of flux density asymmetry, the prediction results are well coincided with measurement ones. As the applications, it can be applied in design for improvement of the $2^{nd}$ harmonic distortion with flux density distribution analysis. The proposed method is expected to be utilized for reducing trial-and-error process in electromagnetic parts design. It can also be used for providing guidelines for parts selection in the early stages.

A Design of DLL-based Low-Power CDR for 2nd-Generation AiPi+ Application (2세대 AiPi+ 용 DLL 기반 저전력 클록-데이터 복원 회로의 설계)

  • Park, Joon-Sung;Park, Hyung-Gu;Kim, Seong-Geun;Pu, Young-Gun;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.4
    • /
    • pp.39-50
    • /
    • 2011
  • In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

A Highly Linear and Efficient DMB CMOS Power Amplifier with Adaptive Bias Control and 2nd Harmonic Termination circuit (적응형 바이어스 조절 회로와 2차 고조파 종단 회로를 이용한 고선형성 고효율 DMB CMOS 전력증폭기)

  • Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.44 no.1
    • /
    • pp.32-37
    • /
    • 2007
  • A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

Reactive Power Control of Single-Phase Reactive Power Compensator for Distribution Line (배전선로용 단상 무효전력 보상기의 무효전력제어)

  • Sim, Woosik;Jo, Jongmin;Kim, Youngroc;Cha, Hanju
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.25 no.2
    • /
    • pp.73-78
    • /
    • 2020
  • In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.