• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.69.2-69
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• 1998

• Transactions on Electrical and Electronic Materials
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• v.13 no.5
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• pp.256-261
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• 2012

Recently, many photovoltaic systems (PV systems) including solar parks and PV farms have been built to prepare for the post fossil fuel era. To investigate the degradation process of the PV systems and thus, efficiently operate PV systems, there is a need to visually monitor PV systems in the range of infrared ray through the Internet. For efficient visual monitoring, this paper explores a multithreaded implementation of a recently developed HEVC standard whose compression efficiency is almost two times higher than H.264. For an efficient parallel implementation under a meshbased 64 multicore system, this work takes into account various design choices which can solve potential problems of a two-dimensional interconnects-based 64 multicore system. These problems may have not occurred in a small-scale multicore system based on a simple bus network. Through extensive evaluation, this paper shows that, for an efficient multithreaded implementation of HEVC intra prediction in a mesh-based multicore system, much effort needs to be made to optimize communications among processing cores. Thus, this work provides three design choices regarding communications, i.e., main thread core location, cache home policy, and maximum coding unit size. These design choices are shown to improve the overall parallel performance of the HEVC intra prediction algorithm by up to 42%, achieving a 7 times higher speed-up.

• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.13-20
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• 1998

고속 디지털 MCM 응용을 위해 MCM-D 와 MCM-SLC 배선에서 CMOS 버퍼의 신호상승시간에 따른 신호전송특성을 연구하였다. 고속신호처럼 버퍼의 내부저항이 배선의 임피던스보다 작아 발생하게 되는 과도한 ringing은 MCM-D와 같이 lossy line의 전송감쇠 효과로 overshooting 이나 undershooting을 줄일 수 있지만 ringing에 의한 신호왜곡을 근 본적으로 막기위해서는 CMOS버퍼와 배선사이에 적절한 종단을 통해 임피던스 비해 크면 배선의 캐패시턴스에 의해 RC 지연이 증가한다. 그런데 MCM-D 배선은 단위길이당 캐패 시턴스도 작고 배선길이를 줄일수 있으므로 총 RC 지연은 MCM-SLC보다 작았다. 결론적 으로 MCM-D 배선이 MCM-SLC 배선에 비해 고속 디지털 MCM기판으로 적합한 것을 알 수 있었다.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.59-64
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• 2002

In this paper, 10$\mu$ m-elevated MEMS CPWs on various substrates are presented. Effective dielectric constants of elevated CPW(ECPW) on polyimide-loaded silicon or alumina substrate are examined and characteristic impedances are also computed versus elevation height. Dispersive property of ECPW and its electromagnetic field distributions are studied through 3-D FDTD algorithm for optimum design. Attenuation of ECPW is measured with TRL calibration procedure and revealed about 3.2 43 lower than that of conventional CPW on the same low-resistivity silicon at 40 CHz. ECPW on polyimide-loaded silicon with overlapped configuration reveals 0.2 dB/mm. Especially, alumina substrate imposes better attenuation than silicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.53-59
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• 2004

This paper proposes an efficient method for computing the 3-dimensional capacitance of complex structures. The proposed method is based on applying numerical 2-dimensional capacitance extraction formula for 3-dimensional interconnect models. This method improves the extraction efficiency 952 times while compromising the accuracy within 1.8 percentage of maximal relative error, compared with the results of Fastcap program for various 3-D models. The proposed method can be used efficiently to extract electrical parameters of on/off-chip interconnects in VLSI systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.483-486
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• 2014

Although flip-chip interconnects have smaller parasitics than bonding wires, they should be carefully designed at 60 GHz. Insertion loss at a flip-chip transition may differ as much as 2 dB depending on design parameters. In this paper we present a comprehensive sensitivity analysis to optimize the flip-chip transition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.270-270
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• 2008

We present details of experimental results in the fabrication of high density line patterns, using imprint technique that can provide a simple and comparatively cost-effective manufacturing means. Barrier array structures for display or interconnects for semiconductor applications were the aims of this study. For pattern fabrication, a polymer layer (Ajinomoto GX-13 dielectric film) with a thickness of 38um that can act as either an insulating or a dielectric layer was laminated on a substrate. Fine tracks were then formed using a patterned stamp under isostatic pressure. The line width was ranged between 10 to 60 mm. A self-assembled monolayer (SAM) of fluorinated alkylchlorosilane [$CF_3(CF_2)5(CH_2)2SiCl_3$] as an anti-sticking layer was coated on the surface of the stamp prior to thermal imprint to improve the de-molding characteristic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.204-209
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• 2016

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.