• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.485-487
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• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• ETRI Journal
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• v.29 no.4
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• pp.437-444
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• 2007

A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultra-wideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-${\mu}m$ CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is $0.9{\times}1.1\;mm^2$.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.270-273
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• 2003

The design, fabrication, and measured result of a 4.7 GHz differential VCO (Voltage Controlled Oscillator) for a 5.2 GHz WLAN (Wireless Local Area Network) applications is presented. The circuit is designed in a 0.35 mm technology employing three metal layers. The design is based on a fully integrated LC tank using spiral inductors. Measured tuning range is 10% of oscillation frequency with a control voltage from 0 to 3.0 V. Oscillation power of $\square$ 2.3 dBm at 4.63 GHz is measured with 21 mA DC current at 3V supply. The phase noise is $\square$ 104.17 dBc/Hz at 1 MHz offset.

• Journal of the Semiconductor & Display Technology
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• v.2 no.1
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• pp.11-14
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• 2003

The high Q(quality factor) suspended spiral inductors were fabricated on the silicon substrate by 3D surface micromachined process. The integration of 2.4GHz VCO has been performed by fabricating suspended spiral inductor of the top of CMOS VCO circuit. The phase noise of VCO integrated MEMS inductor is 93.5 dBc/Hz at 100kHz of offset frequency.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.191-192
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• 2007

This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.6
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• pp.1-5
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• 2011

We present the Multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) technology for increasing the transmission reach of wireless speaker systems. The proposed scheme adopts the Reed-Solomon coding for preventing the random error perfectly and shows the SNR gain in low bit error rate (BER) especially. So, we can increase the maximum reach of MB-OFDM UWB technology since the receiver sensitivity is improved. The simulation environment includes most effects of realistic channel environments such as Additive White Gaussian Noise (AWGN), CM1 channel model, Sampling frequency offset (SFO), Carrier frequency offset (CFO) to improve the simulation accuracy. The simulation results show that the proposed scheme can give a maximum 2 dB SNR gain and increase the transmission reach up to 12.6m.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.357-358
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• 2005

Compact power amplifier modules (PAM) for WCDMA/KPCS and GSM/WCDMA dual-band applications based on multilayer low temperature co-fired ceramic (LTCC) substrates are presented in this paper. The proposed modules are composed of an InGaP/GaAs HBT PAs on top of the LTCC substrates and passive components such as RF chokes and capacitors which are embedded in the substrates. The overall size of the modules is less than 6mm $\times$ 6mm $\times$ 0.8mm. The measured result shows that the PAM delivers a power of 28 dBm with a power added efficiency (PAE) of more than 30 % at KPCS band. The adjacent-channel power ratio (ACPR) at 1.25-MHz and 2.25-MHz offset is -44dBc/30kHz and -60dBc/30kHz, respectively, at 28-dBm output power. Also, the PAM for WCDMA band exhibits an output power of 27 dBm and 32-dB gain at 1.95 GHz with a 3.4-V supply. The adjacent-channel leakage ratio (ACLR) at 5-MHz and 10-MHz offset is -37.5dBc/3.84MHz and -48dBc/3.84MHz, respectively. The measured result of the GSM PAM shows an output power of 33.4 dBm and a power gain of 30.4 dB at 900MHz with a 3.5V supply. The corresponding power added efficiency (PAE) is more than 52.6 %.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1399-1400
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• 2008

본 논문에서는 TSMC 0.18um 공정을 이용하여 2.45GHz 대역에서 동작하는 RFID 리더에 적용 할 수 있는 전압제어 발진기를 설계하였다. 위상 잡음 특성 향상을 위해 PMOS, NMOS 소자를 대칭으로 구성한 complementary cross-coupled LC 발진기 구조로 설계 하였고 MOS 배렉터를 이용하여 주파수를 가변 하였다. 또한 공정에서 사용되는 인덕터에 차폐 도체면(PGS:Patterned Ground Shield) 구조를 삽입했을 때 인덕터의 품질계수가 약 5.82% 향상되었고. 이에 따른 위상 잡음은 1MHz offset 주파수에서 PGS를 삽입하지 않는 구조에서는 -102.666dBc/Hz 이며, PGS 구조를 삽입한 구조는 -104.328dBc/Hz로 약1.662dBc 정도의 성능이 향상 되었다. 전압제어 발진기 Core 사이즈는 900um ${\times}$ 590um이고 주파수 가변 범위는 배렉터 전압 1.2${\sim}$2.1V에서 249MHz로 11.4% 특성을 보였다. 1.8V공급전압에서 5.76mW의 전력소모를 보였다.

• Nuclear Engineering and Technology
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• v.55 no.5
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• pp.1821-1829
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• 2023

The temperature distribution of the reactor pool under natural circulation induced by the RVACS operation was experimentally studied. According to the Bo' based similarity law, which could reproduce the temperature distribution of the working fluid under natural circulation, SINCRO-2D facility was designed based on the PGSFR. It was reduced to 1 : 25 in length scale, having water as a simulant of the sodium, which is the original working fluid. In general, temperature was stratified, however, effect of the natural circulation flow could be observed by the entrainment of the stratified temperature. Relative cooling contribution of the upper plenum (narrow gap) and lower plenum was approximately 0.2 and 0.8, respectively. In the range of decay heat from 0.2% to 1.0%, only the magnitude of the temperature was changed, while the normalized temperature maintained. Boundary temperature distribution change made a global temperature offset of the pool, without a significant local change. Therefore, the decay heat and cooling boundary condition had no significant effect on temperature distribution characteristics of the pool within the given range of the decay heat and boundary temperature distribution.