• Transactions on Electrical and Electronic Materials
• /
• v.1 no.1
• /
• pp.40-44
• /
• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.585-593
• /
• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.69.3-69.3
• /
• 2012

A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.04a
• /
• pp.39-40
• /
• 2008

We have examined post-annealing and passivation for the transparent bottom gate IGZO TFT having an inverse co-planar structure. The oxygen-vacuum two step annealing enhanced the field effect mobility up to 18 $cm^2$/Vsandthesub-threshold swing down to 0.2V/dec. However, the hysterysis and the bias stability problems could not be solved just by post-annealing. Thus, we have passivated the bottom gate IGZO TFTs with organic and inorganic materials. $Ga_2O_3$, $Al_2O_3$, $SiO_2$ and some polymer materials were effective materials for passivations. The hysterysis and the stability of the TFTs were remarkably improved by the passivations. We have manufactured the AMOLED panel with the transparent bottom gate IGZO TFT array successfully.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.551-552
• /
• 2006

Plasma-induced charging damage was been measured during TaN gate electrode of MISFET(TaN/$HfO_2$/Si) or interconnection metal etching step using large antenna structures. The results of these experiments were obtained that $HfO_2$ gate dielectric layer was affected about plasma charging effects and damage increased with F-N tunneling. Therefore, the etching conditions should be optimized to avoid the defects caused by plasma charging.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.6
• /
• pp.409-413
• /
• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• Restorative Dentistry and Endodontics
• /
• v.19 no.2
• /
• pp.611-620
• /
• 1994

The purpose of this study was to evaluate the effect of post space preparation on apical sealing according to the methods and time of gutta percha removal. Forty six extracted single rooted teeth were selected for this study. Forty teeth were used as experimental groups and six teeth as control groups. Forty teeth were routinely prepared by step-back method and obturated with gutta percha cones and zinc oxide-eugenol cement using lateral condensation. All obturated teeth were divided into 4 groups of 10 teeth each. In each group of 1, 2, 3, heated plugger, gate glidden drill and chloroform and K-file were used respectively for post space preparation by removing the gutta percha immediately after obturation. In group 4, post space were prepared with gate glidden drill one week after obturation. In all experimental groups, the post space were prepared so that 4mm of apical gutta percha remained. After post space preparation, apical leakage were measured with electrochemical method for 28 days and analyzed statistically. The following results were obtained ; 1. No statistically significant differences in apical leakage were occured among the experimental groups using heated plugger, gate glidden drill and chloroform and K-file to remove the gutta percha immediately after obturation. 2. No significant difference in apical leakage was found between the teeth prepared post space immediately after obturation and those prepared 1 week after obturation. 3. In all experimental groups, the apical leakage was increased with time passage regardless of the post space preparation time and the gutta percha removal techniques.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• 2002.11a
• /
• pp.13-19
• /
• 2002

Design and implementation methodologies on the performance evaluation system of two-channel ring-core Flux-Gate Compass (FG-Compass) are described, with evaluation procedures and methods based on the polynomial regression models. Performance evaluation system is consists of a step motor driving unit, a bearing transmitting unit and, evaluation programs using polynomial regression formulae. Through performance evaluation tests, total residual deviation tests, total residual deviation of $\pm$4$^{\circ}$ and eigen residual deviation of $\pm$2$^{\circ}$ are obtained from the FG-Compass. The result is more accurate values than the typical FG-Compass with eigen residual deviation of $\pm$4$^{\circ}$ and is provide a possibility to develop a high performance FG-Compass. In addition, the design methodology of a smart FG-Compass with the self estimation and correction of residual deviations is also discussed.

• Journal of Navigation and Port Research
• /
• v.26 no.5
• /
• pp.529-535
• /
• 2002

Design and implementation methodologies on the performance evaluation system of Two-Channel Ring-Core Flux-Gate Compass (TCRC FG-Compass) are described, with evaluation procedures and methods based on the polynomial regression models. Performance evaluation system consists of a step motor driving unit, a bearing transmitting unit and evaluation programs derived from polynomial regression formulae. Newly designed performance evaluation system enabled the accuracy of TCRC FG-Compass to be ascertained. It was confirmed that the size of residual deviation of TCRC FG-Compass is $2^{\circ}$, while that of the conventional one is $4^{\circ}$. In addition, the design methodology to the self estimation and correction of residual deviations is also discussed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.2
• /
• pp.176-183
• /
• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.