• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.185-188
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• 1997

The influence of slow cooling and annealing time in $O_2$ during melting and growth step in MPMG process on J$_{c}$ was investigated. Through the measurement of J$_{c}$ SEM and XRD, it can be observed that the critical characteristics were related with the slow cooling time and annealing time in 02 for melting and growth step of MPMG process. The distribution of critical current density with slow cooling time was the porabolic form and the value of J. was the highest at the 40 hour slow cooling time. And also, the value of J$_{c}$, along the annealing time in $O_2$ in the case of the slow cooling time 40 hour was inclined to increase with annealing time. Consequently, it can be suggested that proper slow cooling titre and annealing time along slow cooling in MPMG process be important to improve the critical characteristics.stics.

• 동력기계공학회지
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• 제2권3호
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• pp.60-67
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• 1998

Edge detection is the first step and very important step in image analysis. We cast edge detection as a problem in cost minimization. This is achieved by the formulation of a cost function that evaluates the quality of edge configurations. The cost function can be used as a basis for comparing the performances of different detectors. This cost function is made of desirable characteristics of edges such as thickness, continuity, length, region dissimilarity. And we use a simulated annealing algorithm for minimum of cost function. Simulated annealing are a class of adaptive search techniques that have been intensively studied in recent years. We present five strategies for generating candidate states. Experimental results(building image and test image) which verify the usefulness of our simulated annealing approach to edge detection are better than other operator.

• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.705-710
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• 1998

Intrinsic gettering is usually to improve wafer quality, which is an important factor for reliable ULSI devices. In order to generate oxygen precipitation in lightly and heavily boron doped silicon wafers with or without high $^75 As^+$ ion implantation, the 2-step annealing method was adopted. After annealing, the were cleaved and etched with th Wright etchant. The morphology of cross section on samples was inspected by FESEM(field emission scanning electron microscopy). The morphology of unimplanted samples was rater rough than that of the implanted. Oxygen precipitation density observed by an optical microscope in lightly boron doped samples was about 3$\times10^6/cm^3$. However, in heavily boron doped samples, the density of oxygen precipitation was largest at $600^{\circ}C$ in 1st annealing, and decreased abruptly until $800^{\circ}C$, But it increased slightly at $1000^{\circ}C$ and was independent with the implantation.

• Journal of Korean Vacuum Science & Technology
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• 제6권2호
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.

• 전자공학회논문지A
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• 제31A권9호
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 C
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• pp.416-418
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• 2000

Thin films of phase-pure perovskite $(Pb_{0.72}La_{0.28})Ti_{0.93}O_3$ (PLT) were deposited in-situ onto Pt/Ti/$SiO_2$/Si substrates by pulsed laser deposition. We have systematically investigated the variation of grain sizes depending on the process condition. Both in-situ annealing and ex-situ annealing treatments have been compared depending on the annealing time. The grain sizes of PLT thin films were successfully controlled 260 to 350 nm by changing process parameters. Microstructural and electrical properties of the film were investigated by C-V measurement, leakage current measurement and SEM. Two-step process to grow $(Pb_{0.72}La_{0.28})Ti_{0.93}O_3$ (PLT) films was adopted and verified to be useful to enlarge the grain size of the film and to enhance the leakage current characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.60-60
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• 2010

1-D nanostructured materials have much more attention because of their outstanding properties and wide applicability in device fabrication. Bismuth oxide($Bi_2O_3$) is an important p-type semiconductor with main crystallographic polymorphs denoted by $\alpha-$, $\beta-$, $\gamma-$, and $\delta-Bi_2O_3$[1]. Due to its unique optical and electrical properties, $Bi_2O_3$ has been extensively investigated for various applications in gas sensors, photovoltaic cells, fuel cells, supercapacitors[2-4]. In this study, $Bi_2O_3$ NWs were grown by two step annealing process: in the first step, after annealing at $270^{\circ}C$ for 10h in a vaccum($3{\times}10^{-6}$ torr), we can obtain the bismuth nanowires. In the second step, after annealing at $300^{\circ}C$ for 2h in $O_2$ ambient, we successfully fabicated $Bi_2O_3$nanowires.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.170-170
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• 1999

We studied Nb growth mode on Cu(100) surface by scanning tunneling microscopy (STM) at room temperature. Nb/Cu is immiscible at room temperature and thus is an ideal system for studying surface alloy formation. Initially deposited Nb atoms are incorporated subsurface on Cu(100). After annealing, they are preferentially found at step edges and appear as bright dots surrounded by dark rings. Ordering emerges from step edges as annealed. Ordered ({{{{ SQRT { 5} }$\times${{{{ SQRT { 5} }}}})R 26.6$^{\circ}$phase Nb structure is formed at $\theta$<0.2ML after annealing to 50$0^{\circ}C$. At higher coverage, $\theta$>0.25, annealing leads to p(2$\times$2) phase. due to large mismatch in lattice parameters, the domain is limited to a few tens of nm2. Growth kinetics of the system will be discussed.

• 대한공업교육학회지
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• 제33권1호
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• pp.249-264
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• 2008

본 연구에서는 저 에너지 이온 주입과 이중 열처리를 통하여 박막 $p^+-n$ 접합을 형성하였고, 보론 확산 모델을 가지고 새로운 시뮬레이터를 설계하여 이온 주입과 열처리 후의 보론 분포를 재현하였다. $BF_2$ 이온을 가지고 실리콘 기판에 저 에너지 이온 주입을 하였고, 이후 RTA(Rapid Thermal Annealing)와 FA(Furnace Annealing)를 통하여 열처리 과정을 수행하였다. 시뮬레이션을 위한 확산 모델은 점결함의 생성과 재결합, BI 쌍의 생성, 보론의 활성화와 침전 현상 등을 고려하였다. FA+RTA 열처리가 RTA+FA 보다 면저항 측면의 접합 특성에서 우수한 결과를 나타내었고, 시뮬레이터에서도 동일한 결과를 나타내었다. 따라서 본 연구를 통하여 박막접합을 형성할 때 열적 효율성을 고려하면 제안된 확산 시뮬레이터와 FA+RTA 공정 방법의 유용성을 기대할 수 있다.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.