• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.6
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• pp.56-63
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• 2004

The real-time NURBS interpolation method using 2-stage interpolation is studied. The 2-stage interpolation method that compensates for interpolation errors within machine BLU is proposed. The interpolation result was filtered by an Acceleration/Jerk limitation equation. Through this 2-stage interpolation, both the interpolation error condition and the motion kinematics could be satisfied. Using computer simulation in which interpolation results are evaluated by a numerical iteration method, it is shown that the 2-stage interpolation algerian could interpolate target curves precisely with geometric and dynamic contentment. The proposed algorithm was implemented in the CNC simulator system and an experimental un was conducted to identify the real-time adaptation.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.8
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• pp.143-151
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• 2004

This paper deals with the precision NURBS interpolator for wire-EDM. Previous research about OAC (Open Architecture Controller) is mostly aimed at NC cutting machines such as milling or lathes, and hence these results are inadequate to apply to wire-EDM. In contradiction to NC machines, wire-EDM operates relatively slow feed rates and based on a feedback control loop to the machining process. The 2-stage interpolation method which reflects wire-EDM specific characteristics was proposed. The constant interpolation error could be acquired through 1 st stage interpolation. Feed rate regulation was performed through 2nd stage interpolation. The suggested algorithm was implemented to test-bed PC-NC system. Computer simulations and the experimental machining were conducted.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of Korea Multimedia Society
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• v.5 no.5
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• pp.494-504
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• 2002

Volume rendering is a method of displaying volumetric data as a sequence two-dimensional image. Because this algorithm has an advantage of visualizing structures within objects, it has recently been used to analyze medical images i.e, MRI, PET, and SPECT. In this paper. we suggested a method for creating images easily from sampled volumetric data and applied the interpolation method to medical images. Additionally, we implemented and applied two kinds of interpolation methods to improve the image quality, linear interpolation and cubic interpolation at the sampling stage. Subsequently, we compared the results of volume rendered data using a transfer function. We anticipate a significant contribution to diagnosis through image reconstruction using a volumetric data set, because volume rendering techniques of medical images are the result of 3-dimensional data.

• Journal of KIISE:Software and Applications
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• v.37 no.7
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• pp.573-577
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• 2010

Image resolution improvement is commonly technique for applications such as image reconstruction or enlargement. It is important to remove image quality degradation such as blocking effect or artificiality occurrence. In this paper, we propose image resolution improvement method using loss information of image. The proposed compute and estimate by low level interpolation of obtained low resolution image, it is applied by interpolated high resolution as 1-stage interpolation. We generate last interpolation image by iteration of error computation and application between obtained low resolution image and 1-stage interpolation image. By experiments using same test images, we confirmed improvement over 3.2dB of average PSNR and enhancement of subject image quality. Also, we can reduce more than 85% computation complexity. The proposed image resolution improvement method may be helpful for various applications of image processing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• The Korean Journal of Applied Statistics
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• v.5 no.2
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• pp.255-268
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• 1992

We propose an iterated interpolation approach for the estimation fo time series parameters in the presence of outliers. The proposed approach iterates the parameter estimation stage and the outlier detection stage until no further outliers are detected. For the detection of outliers, interpolation diagnostic is applied, where the atypical observations by the one-step-ahead predictor instead of downweighting is also proposed. The performance of the proposed estimation methods is compared with other robust estimation methods by simulation study. It is observed that the iterated interpolation approach performs reasonably well is general, especially for single AO case and large $\phi$ in absolute values.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.17-20
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• 2001

This paper studies the channel estimation schemes of Time Division Duplex (TDD) Code Division Multiple Access (CDMA) system with a parallel interference cancellation (PIC) scheme in the multi-Path fading channel. Also, the effective interpolation scheme which maintains the merits of WCDMA TDD mode is proposed. By Monte Carlo simulations, it is shown that the proposed interpolation method can be used in order to obtain the proper performance of a multi-stage PIC and in order to reduce the required Eb/No in the second stage at a BER= 10$^{-2}$

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.10a
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• pp.278-278
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• 2003