• Journal of Power Electronics
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• 제14권2호
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• pp.292-301
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• 2014

This paper presents a new configuration for a three-phase multilevel voltage source inverter. The main bridge is built from a classical three-phase two-level inverter and three bidirectional switches. A variable DC-link employing two unequal DC voltage supplies and four switches is connected to the main circuit in such a way that the proposed inverter produces four levels in the output voltage waveform. In order to obtain the desired switching gate signals, the fundamental frequency staircase modulation technique is successfully implemented. Furthermore, the proposed structure is extended and compared with other types of multilevel inverter topologies. The comparison shows that the proposed inverter requires a smaller number of power components. For a given number of voltage steps N, the proposed inverter requires N/2 DC voltage supplies and N+12 switches connected with N+7 gate driver circuits, while diode clamped or flying capacitor inverters require N-1 DC voltage supplies and 6(N-1) switches connected with 6(N-1) gate driver circuits. A prototype of the introduced configuration has been manufactured and the obtained simulation and experimental results ensure the feasibility of the proposed topology and the validity of the implemented modulation technique.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.438-442
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• 2001

Much attention has given to EMI effects created by variable speed ac drive system. This paper focuses on the switching technique to mitigate common mode voltage. Zero switching states of inverter control invoke large common mode voltage. Using inversed carrier wave, zero switching states are removed. In addition, proposed technique is easy to apply to existing 2-level inverter design. And common mode mitigation technique for sinusoidal PWM is also presented. Proposed switching technique is implemented with a 2.2kw 1735rpm induction motor.

• 전력전자학회논문지
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• 제8권6호
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• pp.478-487
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• 2003

본 논문에서는 고압 대용량 전동기 구동용 멀티레벨 인버터의 종류 및 특징을 간략히 살펴보고, 특히 입출력 전력품질이 우수하고 전압별 시리즈화가 용이한 H-브릿지 멀티레벨 인버터의 구조적 특징 및 장점을 기술하였다. 연구 개발된 3,300V lMVA 용량의 Cascaded H-브릿지 멀티레벨 인버터의 구체적인 전력회로 구조 및 설계방법, 제어기 구성 그리고 PWM 기법을 제시하였다. 또한, 실용량의 시험을 통해 H-브릿지 멀티레벨 인버터는 출력 전압 Step이 여러 단계이고 dv/dt가 적으며 입력단 THD를 크게 낮출 수 있어 성능 면에서도 여타 방식보다 우수함을 입증하였다. 또한 생산적인 측면에서도 저압 소자를 사용하여 설계하므로 기존의 생산/시험 기술과 설비를 이용할 수 있어 매우 경제적이며 Power Cell 단위 결합 구조이므로 신뢰성 측면이나 보수/유지 측면에서도 유리하다는 결론을 얻었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.434-437
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• 2001

Much attention has given to EMI effects created by variable speed ac drive system. This paper focuses on the switching technique to mitigate common mode voltage. Zero switching states of inverter control invoke large common mode voltage. Using inversed carrier wave, zero switching states are removed. In addition, proposed technique is easy to apply to existing 2-level inverter design. Simulation results show that common mode voltages adapting proposed technique are reduced regarding conventional method.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.271-279
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• 2015

Induction cooking application with multiple loads need high power inverters and appropriate control techniques. This paper proposes an inverter configuration with buck-boost converter for multiple load induction cooking application with independent control of each load. It uses one half-bridge for each load. For a given dc supply of $V_{DC}$, one more $V_{DC}$ is derived using buck-boost converter giving $2V_{DC}$ as the input to each half-bridge inverter. Series resonant loads are connected between the centre point of $2V_{DC}$ and each half-bridge. The output voltage across each load is like that of a full-bridge inverter. In the proposed configuration, half of the output power is supplied to each load directly from the source and remaining half of the output power is supplied to each load through buck-boost converter. With buck-boost converter, each half-bridge inverter output power is increased to a full-bridge inverter output power level. Each half-bridge is operated with constant and same switching frequency with asymmetrical duty cycle (ADC) control technique. By ADC, output power of each load is independently controlled. This configuration also offers reduced component count. The proposed inverter configuration is simulated and experimentally verified with two loads. Simulation and experimental results are in good agreement. This configuration can be extended to multiple loads.

• 전기학회논문지
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• 제65권2호
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• pp.319-328
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• 2016

This paper proposes a simplified SVPWM for three level inverters in transformerless photovoltaic (PV) systems. With the proposed SVPWM the three level space vector (SV) diagram is divided into only six sectors as in conventional two level SV diagram in such a way that only seven SVs are used among all the available SVs of three level inverter. The main features of the proposed SVPWM are that it is simple to implement, less switching losses as compared to conventional SVPWM and most importantly it eliminates the leakage currents in transformerless PV systems. Detailed theoretical analysis of the proposed SVPWM are presented and verified by numerical simulations and experimental results.

• 전기전자학회논문지
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• 제26권2호
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• pp.271-279
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• 2022

본 논문은 플로팅 커패시터를 갖는 이중 인버터의 향상된 데드 타임 보상 기법을 제안한다. 플로팅 커패시터를 갖는 이중 인버터는 2-레벨 단일 인버터보다 전력 반도체가 6개가 추가된다. 전력 반도체의 수가 증가로 이중 인버터의 출력 전압은 추가된 전력 반도체의 도통 전압만큼 감소되며 출력 전류 품질은 전력 반도체에 의한 전압 강하와 데드 타임에 의해 저하된다. 본 논문에서 제안하는 기법은 이중 인버터의 데드 타임 및 전력 반도체의 도통 전압을 보상하여 전류 품질을 개선하고 추가적인 대역통과 필터를 이용한 고조파 보상 기법을 통해 데드 타임과 도통 전압 보상에 대한 오차를 추가 보상한다.

• 대한전자공학회논문지
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• 제22권2호
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• pp.75-81
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• 1985

저전류 범위에서 l2L은 연결되는 소자의 input capacitance, resistance 및 그 소자동작에 필요한 전류들에 의해 출력단의 신호가 손상을 입게 되어 logic기능이 방해를 받게 되며 그로 인한 회로의 불확실성이 증가될 수 있다. 본 논문은 이와같은 외부부하와 연결된 I2L-inverter의 기능에 관한 해석을 다루고 rise time과 fall time의 변화에 관한 simulation 및 실험을 통한 측정결과를 비교 분석하였다.

• Journal of Power Electronics
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• 제13권2호
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• pp.243-249
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• 2013

This paper presents a neutral-point voltage balancing method for three-level inverter systems using a time-offset estimation scheme. The neutral-point voltage is balanced by adding a time-offset to the turn-on time of the switches. If an inaccurate time-offset is added, the neutral-point deviation still remains. An accurate time-offset is obtained through the proposed time-offset estimation scheme. This method is implemented without additional hardware, complex calculations, or analysis. The effectiveness of the proposed method is verified by experiments.

• Journal of Electrical Engineering and Technology
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• 제2권4호
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• pp.505-512
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• 2007

The object of this paper is to study a new control structure for sensorless induction machines dedicated to electrical drives using a three-level voltage source inverter VSI-NPC. The amplitude and the rotating speed of the flux vector can be controlled freely. The scheme investigated is an Enhanced direct torque control "EDTC" for electric vehicle propulsion. The considered application imposes some constraints which are achieved in EDTC control (fast torque response, optimal switching logic, torque control at zero speed, and large speed control. The results obtained for an induction motor indicate superior performance over the FOC type without need for any mechanical sensor.