• Geophysics and Geophysical Exploration
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• v.5 no.4
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• pp.299-308
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• 2002

We have derived an analytical expression for the sensitivity of the frequency domain small-loop electromagnetic (EM) surveys over a two-layer earth in order to estimate the depth of investigation with an instrument having the source-receiver separation of about 2 m. We analyzed the sensitivities to the lower layer normalized by those to the upper half-space and estimated the depth of investigation from the sensitivity analyses and the mutual impedance ratio. The computational results showed that the in-phase components of the sensitivity to the lower layer dominates those to the upper layer when the thickness of the upper layer is less than 20 m, while the quadrature components are not sensitive to the lower layer over the entire frequency range. Hence we confirmed that the accurate measurement of the in-phase component is essential to increase the depth of investigation in the multi-frequency small-loop EM survey. When conductive basement of 10 ohm-m underlies the upper layer of 100 ohm-m, an accurate measurement of the in-phase components ensures the depth of the investigation more than 10 m even accounting a noise effect, from which we conclude that the small-loop EM survey is quite effective in imaging the conductive plume down to a considerable depth. On the other hand, in the presence of the resistive basement of 1,000 ohm-m, the depth of investigation may not exceed 5 m considering the instrumental accuracy, which implies that the application of the small-loop EM survey is not recommended over the resistive environment other than detecting the buried conductor.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.951-954
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• 2003

본 논문에서는 고속. 저전력에 적합한 개방 구조를 갖는 8-비트 500Msmaples/s 2-Step ADC 를 제안하였다. 500Msmaples/s 의 고속 동작을 위해서 기존의 M-DAC을 이용한 폐쇄 구조 대신 개방형 구조를 사용하였다. 이와 더불어 저전력을 구현하기 위해서 analog-latch 를 제안하여 동적 동작을 수행시킴으로써 전력 소모를 줄였으며 , mux 의 구현 시 reset switch를 이용하여 로딩 시간을 개선함으로써 high-speed 에 적합하도록 설계하였다. 제안된 ADC 는 1-poly 6-metal 0.18um CMOS 공정을 이용하였으며 1.8V 전원 전압을 이용하여 250mW 의 전력을 소모하며 500M 샘플링 주파수에서 120MHz 신호 입력 시 7.6 비트의 ENOB를 얻을 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.163-169
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• 2016

In this paper, we miniaturized the loop and coil in magnetic resonance wireless power transfer(MR-WPT) system for application to the small mobile device. The proposed disk type double coil resonator was designed to cause resonance at 6.87 MHz. It is composed of thin copper on both-side of acrylic substrate structured 2 mm width, 1 mm pitch and 8 turns. The outer radius of spiral coil pattern is 9 cm. And the proposed loop was made of the copper wire 5 mm diameter of cross-section. The size of loop is 10 cm diameter. For resonance at 6.87 MHz, the capacitor with 3,300 pF was connected in series on the loop. We rearranged the resonators and organized several WPT systems which is rearranged by resonators. The highest transfer efficiency of miniaturized WPT system was 35.67 %. This proposed design of spiral double coil will contribute to make resonator smaller for appling small and thin mobile device.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.171-176
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• 2005

This study designed and fabricated a multi-purpose planar antenna for base stations that are accessible to DCS, WiBro, and ISM. The proposed antenna was designed into an open loop form from the existing monopole structure. The capacitance of the multi-purpose antenna was increased by the coupling of open parts. This makes the use of MMIC and LTCC convenient and the antenna is smaller and has a larger gain than existing antennas. The resonance distance and bandwidth can be adjusted by changing the open gap and the height of the loop of the antenna. The bandwidth of the designed antenna satisfies DCS, IMT-2000, WiBro, Bluetooth, wireless LAN and ISM bands based on VSWR 2. The entire frequency bandwidth is $58.75\%$ of $1.575GHz\~2.985GHz(1.41GHz)$. Also, the radiation pattern of the antenna displayed co-polarization and cross-polarization characteristics at 1.6GHz, 2.3GHz and 2.8GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.25-31
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• 2014

In this paper, a modified Alford loop antenna for on-body communication system is proposed. The proposed antenna operating in the ISM band is designed with consideration of human body effect. One of advantages of the Alford loop antenna structure is low-profile, however the Alford loop antenna is not suitable for on-body devices since it does not have a ground plane for other electronic part of on-body system and requires balanced feeding structure. To be embedded on on-body devices, the proposed antenna is design with the unbalanced feed structure and ground. The performance of the proposed antenna is simulated and measured when it is placed on the human body phantom to consider the effect of the human body. The proposed antenna a 10 dB return loss bandwidth over the ISM band and monopole-like radiation pattern with low-profile. The antenna has the surface of appropriate for on-body communication environment.

• Journal of Ocean Engineering and Technology
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• v.24 no.5
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• pp.88-93
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• 2010

Many pipes that are arranged longitudinally in ships have loops at intervals to prevent the failure of the pipes as they absorb large portions of the axial load caused by the bending of the hull girder and/or thermal loads when the pipes are carrying very hot fluids. Since the loops are curved at corners, an efficient method for conducting the structural analyses of these curved portions is required. In this paper, a pipe loop was analyzed by an analytical method and by the finite-element method in four different ways, i.e., based on straight-beam elements, curved-beam elements, 2-D shell elements, and 3-D solid elements. The results of the five analyses were compared to check the validity of the current curved-beam theory. The paper includes some suggestions on how to analyze the pipe loops efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.3
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• pp.233-238
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• 2003

With the growth of high speed circuit, unwanted system noise is increased and multipoint ground is used to reduce this noise. PCB screw ground structure has radiation noise by ground loop between screws. In order to solve this problem, in this paper, we proposed improved PCB ground structure. Proposed structure improves noise absorption by using microwave absorber and conductive copper tape. We measured radiation PCB noise in the range of 1 ㎓ to 3 ㎓ to investigate proposed structure usefulness. From these results, under 2 ㎓ range proposed structure has noise reduction by 2.62 dBuV/m, which compared with screw ground.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.