• Title/Summary/Keyword: 2진코드

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MPEG-I RVS Software Speed-up for Real-time Application (실시간 렌더링을 위한 MPEG-I RVS 가속화 기법)

  • Ahn, Heejune;Lee, Myeong-jin
    • Journal of Broadcast Engineering
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    • v.25 no.5
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    • pp.655-664
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    • 2020
  • Free viewpoint image synthesis technology is one of the important technologies in the MPEG-I (Immersive) standard. RVS (Reference View Synthesizer) developed by MPEG-I and in use in MPEG group is a DIBR (Depth Information-Based Rendering) program that generates an image at a virtual (intermediate) viewpoint from multiple viewpoints' inputs. RVS uses the mesh surface method based on computer graphics, and outperforms the pixel-based ones by 2.5dB or more compared to the previous pixel method. Even though its OpenGL version provides 10 times speed up over the non OpenGL based one, it still shows a non-real-time processing speed, i.e., 0.75 fps on the two 2k resolution input images. In this paper, we analyze the internal of RVS implementation and modify its structure, achieving 34 times speed up, therefore, real-time performance (22-26 fps), through the 3 key improvements: 1) the reuse of OpenGL buffers and texture objects 2) the parallelization of file I/O and OpenGL execution 3) the parallelization of GPU shader program and buffer transfer.

A 3 V 12b 100 MS/s CMOS DAC for High-Speed Communication System Applications (고속통신 시스템 응용을 위한 3 V 12b 100 MS/s CMOS D/A 변환기)

  • 배현희;이명진;신은석;이승훈;김영록
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.685-691
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    • 2003
  • This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

Damage Tolerance Assessment for Fatigue-Critical Locations of Wing Structure of Aged Aircraft (장기운영 항공기 주익 구조물 피로임계부위의 손상허용평가)

  • Chun, Young-Cheol;Kim, Won-Cheol;Jin, Ji-Won;Chung, Tae-Jin;Kang, Ki-Weon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.41 no.2
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    • pp.129-136
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    • 2017
  • This study aims to assess the damage tolerance of the wing structure of aged aircraft with long-term service through the fatigue crack growth analysis and tests. For the fatigue-critical locations (FCL) W2 and W4 in the wing structure, the fatigue stress spectrum was derived based on a previous study. Thereafter, a crack propagation analysis for the FCLs was conducted using the commercial software $NASGRO^{TM}$. The algorithm for the fatigue stress spectrum was verified. Fatigue crack growth tests were then performed for two types of specimens: Type #1 was extracted from the wing structure of aged aircraft, and Type #2 was made of the same material as the wing structure. By comparing the experimental results of these specimens, we assessed the damage tolerance of the wing structure of aged aircraft with service time.

Modulation Code for Removing Error Patterns on 4-Level NAND Flash Memory (4-레벨 낸드 플래시 메모리에서 오류 발생 패턴 제거 변조 부호)

  • Park, Dong-Hyuk;Lee, Jae-Jin;Yang, Gi-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.12C
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    • pp.965-970
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    • 2010
  • In the NAND flash memory storing two bits per cell, data is discriminated among four levels of electrical charges. We refer to these four levels as E, P1, P2, and P3 from the low voltage. In the statistics, many errors occur when E and P3 are stored at the next cells. Therefore, we propose a coding scheme for avoiding E-P3 or P3-E data patterns. We investigate two modulation codes for 9/10 code (9 bit input and 5 symbol codeword) and 11/12 code (11 bit input and 6 symbol codeword).

Effect of Groove Shape of Blade Tip on Tip Surface Heat Transfer Coefficient Distributions of a Turbine Cascade (블레이드 팁의 Groove 형상이 터빈 캐스케이드 팁 열전달 계수분포에 미치는 영향에 대한 실험적 연구)

  • Nho, Young-Cheol;Jo, Yong-Hwa;Lee, Yong-Jin;Kim, Hark-Bong;Kwak, Jae-Su
    • Journal of the Korean Society of Propulsion Engineers
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    • v.14 no.6
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    • pp.60-68
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    • 2010
  • In this study, the conventional plane tip, double squealer tip, and various groove tip blades were tested in a linear cascade in order to measure the effect of the tip shapes on tip surface heat transfer coefficient distributions. Detailed heat transfer coefficient distributions were measured using a hue-detection based transient liquid crystals technique. Two tip gap clearances of 1.5% and 2.3% of blade span were investigated and the Reynolds number based on cascade exit velocity and chord length was $2.48{\times}10^5$. Results showed that the overall heat transfer coefficients on the tip surface with various grooved tips were lower than those with plane tip blade. The overall heat transfer coefficient on grooved along suction side tip was lower than that on the squealer tip.

Soft-Decision Decoding of the [23,12] Golay Code Using Covering Polynomials (커버링 다항식을 이용한 골레이 부호의 연판정 복호)

  • 성원진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.3A
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    • pp.180-187
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    • 2002
  • The decoding method using covering polynomials is an extended form of error-trapping decoding, and is a simple and effective means to implement decoders for cyclic codes. Covering polynomials can be used for soft-decision decoding as well as for decoding beyond the bounded distance of the code. The implementation complexity is proportional to the number of covering polynomials employed. In this paper, the soft-decision decoding procedure using covering polynomials is described, and the procedure is applied to the [23,12] Golay code. A new set of covering polynomials is derived for the procedure, which is presented as a generalized closed-form solution. The set can be efficiently utilized for decoding a class of cyclic codes including the Golay code. Computer simulation of the described procedure is performed to show the trade-offs between the decoder performance and complexity. It is demonstrated that soft-decision decoding of the Golay code using the derived set of covering polynomials has less than 0.2dB deviation from the optimal performance of maximum-likelihood decoding, with a reduced complexity when compared to the Chase Algorithm 2 combined with hard-decision decoding that has nearly identical performance.

Effect of Groove Shape of Blade Tip on Tip Surface Heat Transfer Coefficient Distributions of a Turbine Cascade (블레이드 팁의 Groove 형상이 터빈 캐스케이드 팁 열전달 계수분포에 미치는 영향에 대한 실험적 연구)

  • Nho, Young-Cheol;Jo, Yong-Hwa;Lee, Youn-Jin;Kim, Hark-Bong;Kwak, Jae-Su
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2010.05a
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    • pp.311-318
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    • 2010
  • In this study, the conventional plane tip, double squealer tip, and various groove tip blades were tested in a linear cascade in order to measure the effect of the tip shapes on tip surface heat transfer coefficient distributions. Detailed heat transfer coefficient distributions were measured using a hue-detection based transient liquid crystals technique. Two tip gap clearances of 1.5% and 2.3% of blade span were investigated and the Reynolds number based on cascade exit velocity and chord length was $2.48{\times}10^5$. Results showed that the overall heat transfer coefficients on the tip surface with various grooved tips were lower than those with plane tip blade. The overall heat transfer coefficient on grooved along suction side tip was lower than that on the squealer tip.

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A Study on Open Source Transition Strategy of Record System (기록시스템의 오픈소스화 전략 연구)

  • An, Dae-jin;Yim, Jin-hee
    • The Korean Journal of Archival Studies
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    • no.52
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    • pp.119-170
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    • 2017
  • This study aims to analyze the environment for the open-source records system and to identify the risk and requirements for the success of the strategy in Korea. For this, Chapter 2 presented a review of the strategic benefits of open source to public organizations, developers, and users. It also discussed the process of cooperatively developing and releasing the source code and the technology infrastructure supporting open source. In Chapter 3, six representative open-source projects in the field of records management were selected, and case studies were conducted. To derive comprehensive implications, we have divided the main development body of open-source projects into international organizations, international cooperation systems, national archives, and software development companies. We also analyzed the background and purpose of each project, the agents of development and funding, the governance model, the development period and cost, the business model and software architecture, the community composition, and the licensing strategy. Through this, we have derived four critical success factors. In terms of technology, a component-based design was required; therefore, we proposed a microservice architecture and a model-view-controller design pattern. Next, it was necessary to reestablish system requirements of records center and archives. Moreover, we also proposed a dual licensing strategy to allow developers to easily participate in open-source projects. Lastly, we emphasized a strong governance structure and an effective cooperation framework to create a sustainable community. For a record system to be open-source successfully in an organization-centered market, the roles of software developers and end users should be exercised more in the community. To achieve this, it is important to build various collaborative tools and development infrastructure from a planning stage to a centralized one.

Comparison of Acidic pH and Temperature Stabilities between Two Bacillus Mannanases Produced from Recombinant Escherichia coli (재조합 대장균으로부터 생산된 Bacillus 속 균주 유래 Mannanases의 내산성과 열안정성 비교)

  • Jeon, Ho Jin;Yoon, Ki-Hong
    • Korean Journal of Microbiology
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    • v.50 no.4
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    • pp.327-333
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    • 2014
  • Two genes encoding the mannanase of Bacillus sp. YB-1401 and B. amyloliquefaciens YB-1402, which had been isolated at acidic pH as mannanase producers, were each cloned into Escherichia coli, and sequenced. Both mannanase genes consisted of 1,080 nucleotides, encoding polypeptides of 360 amino acid residues. The deduced amino acid sequences of the two mannanase genes differed by four amino acid residues different, and were highly homologous to those of mannanases belonging to the glycosyl hydrolase family 26. Comparison of two mannanases produced from recombinant E. coli indicated that His-tagged mannanase of YB-1402 (HtMAN1402) was more stable than that of YB-1401 at acidic pH and high temperature. In particular, HtMAN1402 retained more than 50% of its activity at pH 3.0 after 4 h of pre-incubation, suggesting the enzyme is a valuable candidate for use as a feed additive. In addition, thermostability of the two mannanases was found to be enhanced by $Ca^{2+}$ ions.

VLSI Array Architecture for High Speed Fractal Image Compression (고속 프랙탈 영상압축을 위한 VLSI 어레이 구조)

  • 성길영;이수진;우종호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.4B
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    • pp.708-714
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    • 2000
  • In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

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