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Modulation Code for Removing Error Patterns on 4-Level NAND Flash Memory  

Park, Dong-Hyuk (숭실대학교 정보통신전자공학부 정보저장 및 통신 연구실)
Lee, Jae-Jin (숭실대학교 정보통신전자공학부 정보저장 및 통신 연구실)
Yang, Gi-Ju (동국대학교 정보통신공학과)
Abstract
In the NAND flash memory storing two bits per cell, data is discriminated among four levels of electrical charges. We refer to these four levels as E, P1, P2, and P3 from the low voltage. In the statistics, many errors occur when E and P3 are stored at the next cells. Therefore, we propose a coding scheme for avoiding E-P3 or P3-E data patterns. We investigate two modulation codes for 9/10 code (9 bit input and 5 symbol codeword) and 11/12 code (11 bit input and 6 symbol codeword).
Keywords
2bits/cell NAND Flash Memory; Avoidance Error Pattern Code; E-P3 or P3-E Error Pattern;
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1 J. Lee, S. Hur, and J. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Letters, Vol.23, No.5, pp.264-266, May 2002.   DOI   ScienceOn
2 B. Chen, X. Zhang, and Z. Wang, "Error correction for multi-level NAND flash memory using Reed-Solomon codes," IEEE Workshop on Signal Processing Systems, pp.94-99, Oct. 2008.
3 M. Grossi, M. Lanzoni, and B. Ricco, "Program schemes for multilevel flash memories," Proceeding of the IEEE, Vol.91, No.4, pp. 594-601, April 2003.
4 K. Takeuchi et al., "A source-line programming scheme for low-voltage operation NAND flash memories," IEEE Journal of Solid-State Circuits, Vol.35, No.5, pp.672-681, May 2000.   DOI   ScienceOn
5 S. Satoh et al., "A novel channel boost capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories," Symposium on VLSI Technology Digest of Technical Papers, pp.108-109, June 1998.
6 B. Polianskikh and Z. Zilie, "Induced errorcorrecting code for 2bit-per-cell multi-level DRAM," Proceeding of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, Vol.2, pp.352-355, Aug. 2001.
7 R. Bez et al., "Introduction to flash memory," Proceeding of the IEEE, Vol.91, No.4, pp. 489-502, April 2003.   DOI   ScienceOn
8 조민구, 주영화, 한영수, 진교원, "Disturbanc 에 취약한 패턴 추출 방법," 제 10회 한국테스트학술대회, G-2, 2009년 6월 24일.
9 T. Tanzawa et al., "A compact on-chip ECC for low cost Flash Memories," IEEE Journal of Solid-State Circuits, Vol.32, No.5, pp. 662-669, May 1997.   DOI   ScienceOn
10 K. Takeuchi, T. Tanaka, and T. Tanzawa, "A multipage cell architecture for high-speed programming multilevel NAND flash memories," IEEE Journal of Solid-State Circuits, Vol.33, No.8, pp.1228-1238, Aug. 1998.   DOI   ScienceOn