• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.89-94
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• 2007

For successful implementation of multi-standard transmitter, reconfigurable architecture and component design are essential. This paper presents a reconfigurable CMOS power amplifier designed CMOS 0.25 um process. Designed power amplifier can be operated at 0.9, 1.2, 1.75, and 1.85 GHz. Also, it can be used at 2.4 GHz by using bonding wire inductor. The interstage matching network is composed of two inductors and four switches, and operation frequency can be varied by controlling switches. Proposed power amplifier can be used as a power amplifier in low power applications such as ZigBee or Bluetooth application and used as a driver amplifier in high power application such as CDMA application. Designed power amplifier has 18.2 dB gain and 10.3 dBm output power at 0.9 GHz. Also, it represented 10.3 (18.1) dB gain and 5.2 (10) dBm output power at 1.75 (2.4) GHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.417-423
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• 2012

In this paper, In order to make up for the weak point of driving structure that existing used single motor in motor design, as a method to make use of advantage for joint of hollow type, we propose implementation methods for high torque, high precision, backlash less, and design of secondary safety device, and application method through joint organization using multiple motors.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.1
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• pp.144-153
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• 1997

The determination of the direct kinematics of the parallel mechanism is a difficult problem but has to be solved for any practical use. This paper presents the efficient formulation of the direct kinematics for double parallel robot arm. The robot arm consists of two parallel mechanism, which generate positional and orientational motions, respectively. These motions are decoupled by a passive central axis which is composed of four revolute joints and one prismatic joint. For a set of given lengths of linear actuators, the direct kinematics will find the joint displacements of th central axis from geometric constraints in each parallel mechanism. Then the joint displacements will be converted into the position and the orientation of the end effector of the robot arm. The proposed formulation is decoupled and compacted so that it will be implemented as a real-time direct kinematics. With the proposed formulation, we analyze the motion of the double parallel robot and show its characteristics. Specially, we investigate the workspace in terms of positional space as well as orientational space.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.15 no.1 s.94
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• pp.12-19
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• 2005

This paper proposed a dual actuator using Bimorph PZT for information storage device based on prove array NSOM(near-field scanning optical microscopy). The gap between the media and the optical head should be maintained within the optical tolerance. Therefore, a new actuator having high sensitivity is required. Bimorph PZT, which has fast access time and high sensitivity characteristic, is suitable for this precise actuating system. This paper is focused on derivation of mathematical model of dual Bimorph PZT actuator and control algorithm. Hamilton's principle was used for mathematical model. The model is verified by FEA(finite element analysis), and compared with experimental results. Different control algorithms were used for two Bimorph PZT actuating same direction and opposite direction. The gap between recording media and optical head was controlled within 20nm in experiment.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.89-97
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• 2009

Embedded systems widely used in ubiquitous environments usually employ an event-driven programming model instead of thread-based programming model in order to create a more robust system that uses less memory. However, as the software for embedded systems becomes more complex, it becomes hard to program as a single event handler using the event-driven programming model. This paper discusses the implementation of non-preemptive real-time scheduling theory for the design of embedded systems. To this end, we present an efficient schedulability test method for a given non-preemptive task set using a sufficient condition. This paper also shows that the notion of sub-tasks in embedded systems can overcome the problem of low utilization that is a main drawback of non-preemptive scheduling.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.62-68
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• 1998

In this paper, we proposed the design of the intelligent traffic control system by using multiprocessor architecture. The inter-processor communication of the architecture is implemented by sharing the serial communication channel. In comparing the conventional traffic control system using single processor architecture, the proposed system uses multiple processors controlling the sub systems such as the signal lights, traffic measurement unit, auxiliary signal lights and peripherals. The main processor controls the communication among the processors and the communication protocol link to the central control center at remote site. The proposed architecture reduces the load and simplifies the program of each processor and enables the real time processing of the add-on features of intelligent traffic control systems. The architecture is implemented and the common channel inter-processor communications and the real time operation is experimented .experimented .

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.285-289
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• 1997

발전설비의 대형화로 인하여 소내소비 전력량이 점점 증가하고 있는 추세이며 대용량의 화력발전소라 하더라도 기저부하보다는 부하조정의 역할이 강해져 정격속도로 운전하던 팬, 펌프등을 필요 부하에 따라 회전수를 제어하여 전력절감을 꾀하여야 할 필요가 있다[1]. 이에 따라 생산기술개발 과제로 개발한 대용량 GTO 인버터 시스템을 서 인천복합화력발전소의 3상 6600V 1500KW 용량인 전동기 구동 해수펌프에 적용하기 위한 기술적 검토 내용과 계산된 전력 절감량을 제시하였다. 적용 시스템으로는 개발된 3상 660V 1MVA 단위 인버터를 병렬 운전시켜 2MVA의 용량으로 하였으며 인버터의 입출력 단에 변압기를 설치하여 강압 및 승압 시켜 사용하였다.[2]

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.777-783
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• 2009

In this paper, we implemented a wireless power transmission system at 2.45 GHz. The transmission power is limited within 20 dBm according to the ISM frequency regulations. We used two zero-bias Schottky diode and optimized the RF-DC converter for working a clock at 80 cm distance using a receiver with a single antenna and an Rf-DC converter to reduce parts and cost compared to previously reported literatures.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.