• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.238-242
• /
• 2020

This paper presents a technique using a multilayered dielectric coating to reduce the radar cross section (RCS) value of an integrated mast mounted in a destroyer. The proposed multilayer structure has the advantage of being easy to fabricate because the dielectric constant is defined so that a general dielectric that does not contain a magnetic component that requires high dielectric constant or is frequently used for blocking electromagnetic wave absorption can be used. After applying the proposed multi-layer dielectric structure to the integrated mast shape, the simulation results show that the RCS reduction performance is 10.9dB at 6GHz, 11.95dB at 12GHz, and 11.63dB at 18GHz compared to the structure without the multilayer structure.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2066-2072
• /
• 2014

In this paper, We proposed a UWB microstrip patch antenna with an O-shaped slot of the step structure and analyzed the characteristics of the antenna. In order to improve of frequency properties, size of the patch radiating element, radius change of the O-shaped slot, width of the feed line and a rectangular slot were optimized by CST simulation program. The proposed antenna showed that the 2.8GHz ~ 11.4GHz frequency, the minimum return loss and -10dB bandwidth were -32.39dB and 8.6GHz, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.6
• /
• pp.195-200
• /
• 2018

A W-band frequency octupler is implemented on 100-nm GaAs pHEMT process. The fabricated octupler can be used as a local oscillator or a signal source of W-band transceivers. Three common-source doublers are connected in cascade to multiply an input signal of 10.75 GHz to 83 GHz. A common-source amplifier is followed for each doubler to improve the conversion gain and suppress the unwanted harmonics. The fabricated octupler showes high output of more than 6 dBm in the 80 - 84 GHz band and achieved excellent spurious suppression performance over 20 dBc.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.845-848
• /
• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• Journal of Broadcast Engineering
• /
• v.18 no.3
• /
• pp.491-494
• /
• 2013

This paper proposes a stochastic/dynamic routing protocol which aims the minimization of the summation of time average expected power expenditure with buffer stability in mobile ad-hoc 60 GHz wireless networks. By using 60 GHz RF, the wireless devices can transmit/receive 1080p HD video signals without compression. In addition, our algorithm works without centralized controller, so that the distributed operation is available. The novelty of the proposed algorithm was also verified by simulations.

• Journal of electromagnetic engineering and science
• /
• v.18 no.4
• /
• pp.215-220
• /
• 2018

This study presents a dual-band polarization-reconfigurable antenna that comprises a large square patch with a pair of corner-cut edges and two small square patches with a shorting via. Two PIN diodes are located between the large square patch and two small square patches. Depending on the bias state applied to the two PIN diodes, each small patch may be disconnected or connected to the large square patch. As a result, the proposed antenna can provide polarization reconfigurability between two orthogonal linear polarizations. Further, the proposed antenna operates at 2.51 GHz and 2.71 GHz. From the measured results, the proposed antenna shows a 10 dB bandwidth of 2.39% (2.49-2.55 GHz) and 2.58% (2.68-2.75 GHz). In this work, the frequency ratio can be easily controlled by changing the size of the small patch.

• Journal of electromagnetic engineering and science
• /
• v.18 no.2
• /
• pp.141-143
• /
• 2018

Two 110-GHz oscillators have been developed in 65-nm CMOS technology. To study the effect of layout on the circuit performance, both oscillators had the same LC cross-coupled topology but different layout schemes of the circuit. The oscillator with the conventional cross-coupled design (OSC1), showed an output power of -3.9 dBm at 111 GHz with a phase noise of -75 dBc/Hz at 1-MHz offset. On the other hand, OSC2, with a modified cross-coupled line layout, generated an output power of -2.0 dBm at 117 GHz with a phase noise of -77 dBc/Hz at 1-MHz offset. The result indicates that the optimized layout can improve key oscillator performances such as oscillation frequency and output power.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.7
• /
• pp.944-950
• /
• 1993

Diodes and GaAs have been commonly used in a mixer design until recently. However, diodes are not preferred to use at the front-end of DBS receiver due to the conversion loss large noise. HEMT has larger conversion gain and better noise characteristics comparing with GaAs MESFET. This paper describes the design procedure, structure, and performance of a mixer, utilizaing HEMT designed by OKI Co. . A mixer configuration in which the local oscillator(LO) signal is applied to the gate is used. When the LO power is 0.01 dBm, the conversion gain of 3.7dB is obtained at IF and the 3 dB bandwidth is 400MMz.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.45 no.2
• /
• pp.37-44
• /
• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of Advanced Navigation Technology
• /
• v.28 no.1
• /
• pp.136-141
• /
• 2024

In this paper, a broadband inset-fed microstrip patch antenna operating at 10.525 GHz band was proposed. The proposed broadband inset-fed microstrip patch antenna consists of three narrow rectangular patches. At the center of the center patch, two symmetrical side patches were connected by a strip conductor and were arranged with their centers shifted in a perpendicular direction with respect to the center patch. For performance comparison, a conventional inset-fed square microstrip patch antenna was designed. Experiment results show that the frequency band of the measured input reflection coefficient with a voltage standing wave ratio less than 2 for the broadband inset-fed microstrip patch antenna was 10.036-11.051 GHz (9.63%), whereas that for the conventional inset-fed rectangular microstrip patch antenna was 10.306-10.772 GHz (4.42%). Therefore, the input reflection coefficient frequency bandwidth of the fabricated broadband inset-fed microstrip patch antenna was increased by 2.18 times, compared to the conventional inset-fed square microstrip patch antenna.