• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.815-817
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• 2012

본 논문에서는 차량 충돌 예방 레이더 시스템-온-칩용 77GHz 고주파 전단부(RF front-end)를 제안한다. 이러한 고주파 전단부는 77GHz의 동작주파수를 가진 저 잡음 증폭기와 고주파 전력 증폭기로 구성된다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 저잡음 증폭기의 경우 전압이득이 36dB로 최근 발표된 연구결과 중 가장 우수한 수치를 보였다. 전력 증폭기는 포화전력과 출력 $P_{1dB}$이 18dBm과 15dBm으로 기존 연구결과 중 가장 우수한 결과를 각각 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.251-258
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• 2023

In this paper, we propose DLP(Dual Linear Polarization) stack antenna for private network. The proposed antenna has general stack structure and design airgap between two substrate to obtain the maximum gain. Also, to improve cross polarization isolation, two feeding port is designed to separate for each substrate. The size of each patch antenna is 17.80 mm(W1)×16.70 mm(L1) for lower patch and 18.56 mm(W2)×18.73 mm(L2) for upper patch, which is designed on the FR-4 substrate which thickness (h) is 1.6 mm, and the dielectric constant is 4.3, and which is 40.0 mm(W)×40.0 mm(L) for total size of substrate. From the fabrication and measurement results, bandwidths of 100 MHz (4.74 to 4.84 GHz) for feeding port 1, and 150 MHz (4.67 to 4.82 GHz) for feeding port 2 are obtained on the basis of -10 dB return loss and transmission coefficient S21 is got under the -20 dB. Also, cross polarization isolation between each feeding port obtained

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.704-709
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• 2007

In this paper, a CPW band-pass filter with a rejection band is proposed for UWB(Ultra-Wideband) communication systems. The proposed filter has a band-pass characteristic of wide-band by inserting only a slot in $50{\Omega}$ transmission line. To obtain the band-rejection function at WLAN frequency band($5.15{\sim}5.725GHz$), the designed filter is combined with folded slot resonators on the ground plane of the CPW structure. The fabricated CPW band-pass filter shows a compact size of $15.35{\times}13.60mm$, a wide passband of 2.8 GHz to 9.8 GHz and the narrow stop-band of 5.15 GHz to 5.71 GHz for 3-dB bandwidth. Also, the measured group delay is less than 400 psec throughout the operation frequency band except the rejection band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.4
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• pp.628-635
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• 1999

At center frequency of 11.85 GHz, wideband left-handed circularly polarized microstrip array antenna is designed with the method of sequential ratation based on $2\times2$ radiation elements($0^{\circ}$, $45^{\circ}$, $90^{\circ}$, $135^{\circ}$ phase delay). Its return loss, axial ratio bandwidth, radration pattern, and gain are compared with those adopting sequential rotation based on $1\times2$ radiation elements($0^{\circ}$, $90^{\circ}$, $180^{\circ}$, $270^{\circ}$phase delay). The $8\times8$ array is manufactured and measured. The results show that 10 dB return loss bandwidth is 10.51~12.74GHz(18.82%) which is 1.57 times wider than the case using $1\times2$ sequential rotation method, 3 dB axial ratio bandwidth is 11.43~12.5 GHz(9.03%) which is 1.25 times as wide as that using $1\times2$ sequential rotation method and the antennal gain is 25.4 dB. The results of mesurements are almost similar to those of simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.82-89
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• 2007

This paper presents a coplanar waveguide fed L-planar type monopole antenna which covers ultra wideband(UWB) region of 3.1 GHz to 10.6 GHz. The proposed UWB L-planar type monopole antenna is designed and implemented on the organic substrates( ${\varepsilon}_{r}=3.38,\;@10\;GHz$). The radiation elements, feed line, and ground planes of the antenna are printed on the same conductive layer of the substrates. The bandwidth of the proposed antenna is measured in the range of 3.0 GHz to 11.0 GHz. The measured radiation patterns are symmetrical in E-plane and omni-directional in H-plane. Antenna gains ranges from 1.4 dBi to 4.6 dBi. The proposed UWB antenna shows that the structure is adequate for the design of RFIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2351-2358
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• 2014

In this paper, a design method for a compact CPW-fed slot antenna using SRRs is studied. The structure of the proposed slot antenna is a rectangular slot antenna loaded with SRR conductors inside the slot to reduce the antenna size. Optimal design parameters are obtained by analyzing the effects of the gap between the SRR conductors and slot, and the width of the SRR conductors on the input VSWR characteristic. The optimized compact slot antenna operating at 2.45 GHz band is fabricated on an FR4 substrate with a dimension of 36 mm by 30 mm. The length of the proposed compact slot antenna is reduced to 14.3% compared to that of a conventional rectangular slot antenna. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.4-2.49 GHz for a VSWR < 2, and measured gain of 2.3 dBi at 2.45 GHz.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.198-201
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• 2001

L자형 루프를 이용하여 주파수대역이 6-18 GHz인 동축-이중릿지도파관 변환기를 상용 소프트웨어인 HFSS를 이용하여 설계한 후 제작하였다. L자형 루프는 동축-구형도파관 변환기에 이미 이용되고 있는 구조로써, 이를 동축-이중릿지도파관 변환기에 적용한 것이다. 제작 후 측정결과 대역폭이 6-18 GHz로 3:1 이상을 만족하며, 최대 삽입손실이 -1.52 dB 이었다.