• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.372-383
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• 2011

This paper proposes an improved design of an interleaved motion vector coding scheme with flexibility in predictive motion vector component by exploiting motion characteristics. It can use component-wise adaptive motion vector predictor based on the utility of spatial and temporal motion field without any signaling bit for indicating decoder of the selected predictive motion vector component. Experiment with test video data shows about 1.99% (max 8.71%) bit rate reduction compared to the conventional H.264/AVC method.

• Transactions of the Society of Information Storage Systems
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• v.3 no.2
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• pp.94-112
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• 2007

Nano-sized inverted domain dots in ferroelectric materials have potential application in ultrahigh-density rewritable data storage systems. Herein, a data storage system is presented based on scanning non-linear dielectric microscopy and a thin film of ferroelectric single-crystal lithium tantalite. Through domain engineering, we succeeded to form an smallest artificial nano-domain single dot of 5.1 nm in diameter and artificial nano-domain dot-array with a memory density of 10.1 Tbit/$inch^2$ and a bit spacing of 8.0 nm, representing the highest memory density for rewritable data storage reported to date. Sub-nanosecond (500psec) domain switching speed also has been achieved. Next, long term retention characteristic of data with inverted domain dots is investigated by conducting heat treatment test. Obtained life time of inverted dot with the radius of 50nm was 16.9 years at $80^{\circ}C$. Finally, actual information storage with low bit error and high memory density was performed. A bit error ratio of less than $1\times10^{-4}$ was achieved at an areal density of 258 Gbit/inch2. Moreover, actual information storage is demonstrated at a density of 1 Tbit/$inch^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.26-32
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• 2012

In this study, we proposed an intelligent algorithm for the performance improvement of ASK system for giga-bit modem in millimeter band. The proposed intelligent algorithm is a fuzzy logic system. The inputs to the fuzzy logic system are the remainder and integral of remainder that occurred counter of receiver, and the output is bandwidth of LPF. In order to verify the effectiveness of the proposed method, simulation is performed to the proposed system and the fixed bandwidth system, and is confirmed to the BER performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.362-369
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• 2007

APSK (Amplitude Phase Shift Keying) digital modulation is characterized by the circular positioning of the transmission symbols in the constellation diagram. Due to such structural characteristics, the peak-to-average power ratio of the APSK modulation is lower than that of the QAM (Quadrature Amplitude Modulation), and the amount of performance degradation over nonlinear channels can be mitigated. The APSK modulation scheme has recently been adopted as satellite communication system standards including the DVB-S2 (Digital Video Broadcasting - Satellite, Version 2). In this paper, a BER (Bit Error Rate) upper bound approximation formula is derived using the channel model with the output power saturation characteristics, and its accuracy is demonstrated. Using the derived formula, the input power level that minimizes the BER is determined. The optimized performance based on the radii ratio of the 16APSK constellation and the channel saturation level is also presented.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.198-202
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• 1988

In digital mobile communications received speech data are affected by burst errors as well as random errors. To overcome these errors we propose a bit-selective forward error correction scheme for the speech data which is sub-band coded at 13 kbps and transmitted over a 16 kbps channel. For a few error correcting codes the signal-to-noise ratio of error-corrected speech is obtained and compared through the simulation of mobile communication channels.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1182-1188
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• 2005

In this paper, various power delay profiles (PDP) are simulated to study the influence of the PDP shape on the bit error rate (BER) performance of Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Assuming Rayleigh fading with 16-QAM modulation scheme, the simulation focuses on the investigation of the various shapes of the PDP which are often characterized by peaks, slope, attenuation and distance of an echo profile of waves. This yields information about the properties of the channel, and can be applied to decide the performance of the systems according to the channel.