• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.2
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• pp.149-154
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• 2004

In this research, we selected the speech recognition to implement the electric wheelchair system as a method to control it by only using the speech and used DTW (Dynamic Time Warping), which is speaker-dependent and has a relatively high recognition rate among the speech recognitions. However, it has to have small memory and fast process speed performance under consideration of real-time. Thus, we introduced VQ (Vector Quantization) which is widely used as a compression algorithm of speaker-independent recognition, to secure fast recognition and small memory. However, we found that the recognition rate decreased after using VQ. To improve the recognition rate, we applied ART2 (Adaptive Reason Theory 2) algorithm as a post-process algorithm to obtain about 5% recognition rate improvement. To utilize ART2, we have to apply an error range. In case that the subtraction of the first distance from the second distance for each distance obtained to apply DTW is 20 or more, the error range is applied. Likewise, ART2 was applied and we could obtain fast process and high recognition rate. Moreover, since this system is a moving object, the system should be implemented as an embedded one. Thus, we selected TMS320C32 chip, which can process significantly many calculations relatively fast, to implement the embedded system. Considering that the memory is speech, we used 128kbyte-RAM and 64kbyte ROM to save large amount of data. In case of speech input, we used 16-bit stereo audio codec, securing relatively accurate data through high resolution capacity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.61-69
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• 2012

Smart Grid is the next-generation intelligent power grid that maximizes energy efficiency with the convergence of IT technologies and the existing power grid. Smart Grid is created solution for standardization and interoperability. Smart Grid industry enables consumers to check power rates in real time for active power consumption. It also enables suppliers to measure their expected power generation load, which stabilizes the operation of the power system. Smart industy was ecolved actively cause Wireless communication is being considered for AMI system and wireless communication using ZigBee sensor has been applied in various industly. In this paper, we proposed efficient addressing scheme for improving the performance of the routing algorithm using ZigBee in Smart Grid environment. A distributed address allocation scheme used an existing algorithm has wasted address space. Therefore proposing x, y coordinate axes from divide address space of 16 bit to solve this problem. Each node was reduced not only bitwise but also multi hop using the coordinate axes while routing than Cskip algorithm. I compared the performance between the standard and the proposed mechanism through the numerical analysis. Simulation verify performance about decrease averaging multi hop count that compare proposing algorithm and another. The numerical analysis results show that proposed algorithm reduce multi hop than ZigBee distributed address assignment and another.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.6
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• pp.4125-4130
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• 2015

This paper presents the communication performance for the radiation pattern reconfigurable antenna in the wearable device measuring bio signal (temperature, blood pressure, pulse etc.) of human body. The operational frequency is 2.4 - 2.5 GHz, which covers Bluetooth communication bandwidth. The maximum gain of the antennas is 1.96 dBi. The proposed antenna is efficiently transmitting and receiving signal by generating two opposite beam directions using two RF switches (PIN diode). Also, we investigated how radiation pattern changes according to three angles ($30^{\circ}$, $90^{\circ}$, $150^{\circ}$) of Top Loading. In this paper, we measured and compared the SNR (Signal-to-Noise Ratio) and BER (Bit Error Rate) performances of the proposed antennas in the condition between an ideal environment of anechoic chamber and smart house existing practical electromagnetic interferences (Universal Software Radio Peripheral, USRP). Throughout the comparing the results of the measurement of two cases, we found that the SNR is degraded over 5dB in average and BER is increased over ten times in maximum, therefore, it is confirmed that the error rate of receiving signal is increased. The measured results of SNR and BER value in this paper able to expect the performance degrading by the interference from the electromagnetic devices.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.285-290
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• 2023

Compressors are widely used in high-speed electronic systems and are used to reduce the number of operands in multiplier. The proposed compressor is constructed based on the m-GDI(: modified gate diffusion input) to reduce the propagation delay time. This paper is compared the performance of compressors by applying 4-2, 5-2 and 6-2 m-GDI compressors to the multiplier, respectively. As a simulation results, compared to the 8-bit Dadda multiplier using the 4-2 and 6-2 compressor, the multiplier using the 5-2 compressor is reduced propagation delay time 13.99% and 16.26%, respectively. Also, the multiplier using the 5-2 compressor is reduced PDP(: Power Delay Product) 4.99%, 28.95% compared to 4-2 and 6-2 compressor, respectively. However, the multiplier using the 5-2 compression circuit is increased power consumption by 10.46% compared to the multiplier using the 4-2 compression circuit. In conclusion, the 8-bit Dadda multiplier using the 5-2 compressor is superior to the multipliers using the 4-2 and 6-2 compressors. The proposed circuit is implemented using TSMC 65nm CMOS process and its feasibility is verified through SPECTRE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.78-83
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• 2000

Vocoders used in digital mobile phone adopt new improved algorithm to achieve better communication quality. Therefore the communication problem occurs between mobile phones using different vocoder algorithms. In this paper, the efficient implementation of 8kbps and 13kbps QCELP into one DSP chip to solve this problem is presented. We also describe the optimization method at each level, that is, algorithm-level, equation-level, and coding-level, to reduce the complexity for the QCELP vocoder algorithm implementation. The complexity in the codebook search-loop that is the main part for the QCELP algorithm complexity can be reduced about 50% by using these optimizations. The QCELP implementation with our DSP requires only 25 MIPS of computation for the 8kbps and 33 MIPS for the 13kbps ones. The DSP for our real-time implementation is a 16-bit fixed-point one specifically designed for vocoder applications and has a simple architecture compared to general-purpose ones in order to reduce the power consumption.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.41-47
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• 2016

The times of multiplication for encryption and decryption of cryptosystem is primarily determined by implementation efficiency of the modular exponentiation of $a^b$(mod m). The most frequently used among standard modular exponentiation methods is a standard binary method, of which n-ary($2{\leq}n{\leq}6$) is most popular. The n-ary($1{\leq}n{\leq}6$) is a square-and-multiply method which partitions $b=b_kb_{k-1}{\cdots}b_1b_{0(2)}$ into n fixed bits from right to left and squares n times and multiplies bit values. This paper proposes a variable-length partition algorithm that partitions $b_{k-1}{\cdots}b_1b_{0(2)}$ from left to right. The proposed algorithm has proved to reduce the multiplication frequency of the fixed-length partition n-ary method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.201-206
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• 2016

Aircraft have a cross axis of the three each other for maintenance of aircraft position. It is called roll axis, pitch axis and yaw axis. Attitude reference system is a sensor for detecting a change of the three axis. In this paper, mobile robot platform install part of Pan-tilt and HMD attitude reference system, because of we use control camera. The acceleration sensor is very weak a lot of noise to vibration, also problem with data from process of mapping to the data problems to arise. However to solve this problem, we removed the average filter and Cosine Interpolation for Pan-tilt. Using capacity evaluation for outdoor environment for we are proposing. Mobile robot has HMD and equipped Pan-tilt. We control mobile robot camera. In this experiment result is little bit delay happening, however Pan-tilt camera is relatively stable control checking. Also, we will checking any terrain and slopes is no problem for mobile robot driving skills.