• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.933-939
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• 2010

In this paper, modified spiral monopole printed antenna for dual band operation in GPS(1.57~1.577 GHz) and WiBro(2.3~2.4 GHz), WLAN(2.4~2.48 GHz) is proposed. To control the frequency ratio of the antenna for dual band operation freely, distance between inner lines of the spiral is diversified by using the different current distribution between basic resonance frequency of spiral monopole antenna and harmonic resonance frequency$(3\lambda_H/4)$. And also the branch line is inserted. Bandwidth(-10 dB) of the antenna is measured 140 MHz(1.47~1.61 GHz) in basic resonance frequency and 420 MHz(2.29~2.71 GHz) in harmonic resonance frequency$(3\lambda_H/4)$. The peak antenna gains are measured 2.825 dBi in GPS(1.57 GHz), and 3.65 dBi in WiBro(2.35 GHz), and 4.564 dBi in WLAN(2.44 GHz).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.4 no.3
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• pp.11-17
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• 1993

An active diplexer can be realized by using a MESFET and 2-sections of asymmetrical coupled bandpass filter, where the admittance inverter parameters in equivalent circuit of asym- metrical coupled microstrip lines are given as a function of an fundamental design parameter of a bandpass filter. An experimental active diplexer was designed over 22 and 18 percent bandwidth centered at 9 GHz and 11 GHz respectively, and the design data was optimized by Super-Compact. The gain performance was $6.2\pm0.3$dB in each band of 8.3~9.6 GHz and 10.3~11.8 GHz The measured bandwidth of the active diplexer was closely matched to design data but measured gain was slightly lower (1.5 dB) than the designed value.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.535-540
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• 2004

In this paper, We proposed a rectangular slot antenna with CPW feeder. Slot antennas fed by CPW are attractive due to the simple fabrication simplicity and ease of integration with active devices. This antenna consists of two parts, inner patch and outer patch to realize wide-band antenna by multi-frequency. Also, We fabricated a proposed rectangular slot antenna, confirm characteristics of multi-frequency by tuning antenna parameters, inner antenna's location and size. The experimental results show that each resonant frequency of a fabricated antenna is measured at almost 1, 9GHz, 2.8GHz, 3, 5GHz, 4, 9GHz. In radiation patterns each resonant frequency, radiation pattern 4-th resonant frequency is the same ad that of TM11 in patch antenna. Therefore, the experimental and theoretical results shows that a proposal rectangular slot antenna have triple resonant frequencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.117-122
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• 2006

A CMOS LNA based on a single-stage cascode configuration is designed for MB-OFDM ultra-wide band(UWB) systems. Wideband($3.1GHz\~4.9GHz$) input matching is performed using a simple bandpass filter to minimize the chip size and the noise figure degradation. The simulation results using $0.18{\mu}m$ CMOS process parameters show a power gain of 9.7dB, a 3dB band width of $2.1GHz\~7.1GHz$, a minimum NF of 2dB, an IIP3 of -2dBm. better than -11.8dB of input matching while occupying only $0.74mm^2$ of chip area. It consumes 25.8mW from a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.739-745
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• 2009

This paper presents a design for trapezoidal planar UWB(Ultra Wide-band) antenna using symmetry meander line to realize broad bandwidth at low frequency region. The size of proposed design antenna is $15.5{\times}21{\times}1.6mm^3$ and dielectric substrate considered in design has 4.4 of relative permittivity. The calculated bandwidth is from 1.31 GHz to 10.83 GHz and the measured return loss is 1.5 GHz to 10.6 GHz at -10 dB below, and satisfies with the UWB antenna's bandwidth. The simulated and measured radiation patterns show fine agreement with each other at each frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.997-1002
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• 2009

This Letter presents a wideband ENG(Epsilon Negative) ZOR(Zeroth-Order Resonant) antenna designed on a microstrip line. It has a mushroom structure and its size is only $7.65{\times}1.31{\times}2.37\;mm$(or $0.306{\times}0.053{\times}0.095\;{\lambda}_0$ at 12 GHz) owing to zeroth-order resonance. The design procedures with closed form solutions are provided using transmission line theory considering radiation loss. The measured antenna bandwidth is about 20.0 % at 9.2 GHz and antenna gain is 7.1 dBi despite the compact size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.849-852
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• 2007

In this paper, the high gain and the broadband microstrip patch antenna, which is applicable to 5 GHz band wireless LAN, is designed in order to integrate IEEE 802.11a's detailed standards($a:5.15{\sim}5.25$, $b:5.25{\sim}5.35$, $c:5.725{\sim}5.875$ [GHz]). Designed patch antenna has settled resonance frequency by insert substance(polyurethane: ${\varepsilon}_r=6.5$) between the separated parasitic patch and radiation patch for the purpose of miniaturize. And the form (${\varepsilon}_r=1.03$) were to fix the separated radiation patch and ground plans by air. Designed frequency bandwidth(VSWR 2:1) of the antenna showed broadband characteristic of $4.9[GHz]{\sim}6.1[GHz]$ to about 1.2[GHz]. Also the E-plan and H-plan profit 12[dBi] above, the 3[dB] beamwidth showed the characteristic over the E-plan $30^{\circ}$ and H-plan $60^{\circ}$ to be improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.137-146
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• 2009

We present a micromechanical digital-to-analog (DA) variable capacitor using a parallel digital actuator array, capable of accomplishing high-Q tuning. The present DA variable capacitor uses a parallel interconnection of digital actuators, thus achieving a low resistive structure. Based on the criteria for capacitance range ($0.348{\sim}1.932$ pF) and the actuation voltage (25 V), the present parallel DA variable capacitor is estimated to have a quality factor 2.0 times higher than the previous serial-parallel DA variable capacitor. In the experimental study, the parallel DA variable capacitor changes the total capacitance from 2.268 to 3.973 pF (0.5 GHz), 2.384 to 4.197 pF (1.0 GHz), and 2.773 to 4.826 pF (2.5 GHz), thus achieving tuning ratios of 75.2%, 76.1%, and 74.0%, respectively. The capacitance precisions are measured to be $6.16{\pm}4.24$ fF (0.5 GHz), $7.42{\pm}5.48$ fF (1.0 GHz), and $9.56{\pm}5.63$ fF (2.5 GHz). The parallel DA variable capacitor shows the total resistance of $2.97{\pm}0.29\;{\Omega}$ (0.5 GHz), $3.01{\pm}0.42\;{\Omega}$ (1.0 GHz), and $4.32{\pm}0.66\;{\Omega}$ (2.5 GHz), resulting in high quality factors which are measured to be $33.7{\pm}7.8$ (0.5 GHz), $18.5{\pm}4.9$ (1.0 GHz), and $4.3{\pm}1.4$ (2.5 GHz) for large capacitance values ($2.268{\sim}4.826$ pF). We experimentally verify the high-Q tuning capability of the present parallel DA variable capacitor, while achieving high-precision capacitance adjustments.