• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.9
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• pp.54-62
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• 2007

In this paper, a novel wideband notched compact UWB antenna is designed to satisfy the licensed UWB frequency bandwidth($3.1{\sim}4.8$ GHz, $7.1{\sim}10.2$ GHz) by symmetrically arranging two adjacent sectorial loop antennas. The wideband($4.8{\sim}7.1$ GHz) notch can be obtained by inserting the inverted-L shaped slits on the patch. The designed UWB antenna has return loss lower than -10dB at 3.1 GHz and over, group delay value lower than 1 ns and the linear phase property. The optimized UWB antenna inserted the inverted-L shaped slits has return loss great than -10dB, 5 ns of group delay, nonlinear phase and decreased gain properties over the frequency band, 4.8 GHz to 7.1 GHz.

• The Bulletin of The Korean Astronomical Society
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• v.22
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• pp.8.1-8.1
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• 1997

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.4 no.3
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• pp.11-17
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• 1993

An active diplexer can be realized by using a MESFET and 2-sections of asymmetrical coupled bandpass filter, where the admittance inverter parameters in equivalent circuit of asym- metrical coupled microstrip lines are given as a function of an fundamental design parameter of a bandpass filter. An experimental active diplexer was designed over 22 and 18 percent bandwidth centered at 9 GHz and 11 GHz respectively, and the design data was optimized by Super-Compact. The gain performance was $6.2\pm0.3$dB in each band of 8.3~9.6 GHz and 10.3~11.8 GHz The measured bandwidth of the active diplexer was closely matched to design data but measured gain was slightly lower (1.5 dB) than the designed value.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2489-2497
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• 1994

This paper presents the development of a 10 W solid-state hybrid power amplifier(SSPA). operating over $7.7\sim8.5GHz$. The fabrication and measurement of this amplifier are performed with 3 sections, such as the front one for high gain, the middle one for driving, and high power one, to minimize the risk of failure and to increase the easiness of development. and then the final amplifier is realized by connecting 3 sections above mentioned, DC bias circuit, and temperature compensation circuit on one housing. Total small signal gain obtained is about $45\pm1dB$, the input and output return losses are 25 and 27 dB respectively. The output power measured at 1 dB gain compression point for 3 frequencies at 7.7, 8.1, and 8.5 GHz are $39.8\sim40.4dBm$, which is about 10 W. and the 3rd-order harmonic powers of 2 tones test are 13.34 dBc at output power 37.5 dBm. These obtained results satisfies the initially required specification. and the realized SSPA can be installed as a subsystem of the microwave transponder for telecommunication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.924-927
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• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

• Journal of Navigation and Port Research
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• v.31 no.6
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• pp.503-507
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• 2007

In this paper, the ultra-widebend, microstrip patch antenna with the bandwidth of 3 GHz was implemented for ultra-wideband(UWB) wireless communication applications. In order to cover the very wide bandwidth of 3 GHz, a multi-resonance antenna was designed, each resonance frequency was separated into five frequency bend, 7.5, 8.1, 8.7, 9.3, and 9.9GHz with the interval of 600MHz BW. And for wideband characteristics of each antenna, U-slot antennas were designed at each center frequency. Designed five U-slot antennas were connected in series for multi-resonance of 3GHz BW and wideband matching was also designed for impedance matching transmission line calculated. The relative dielectric constant, the height, the loss tangent of the PCB substrate were ${\epsilon}_r=4.8,\;h=0.6$ and loss tangent=0.0009 respectively. The implemented antenna's radiation patterns and gain were directivity characteristics and $1.46{\sim}4.08dBi$ at the five separated center frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.739-745
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• 2009

This paper presents a design for trapezoidal planar UWB(Ultra Wide-band) antenna using symmetry meander line to realize broad bandwidth at low frequency region. The size of proposed design antenna is $15.5{\times}21{\times}1.6mm^3$ and dielectric substrate considered in design has 4.4 of relative permittivity. The calculated bandwidth is from 1.31 GHz to 10.83 GHz and the measured return loss is 1.5 GHz to 10.6 GHz at -10 dB below, and satisfies with the UWB antenna's bandwidth. The simulated and measured radiation patterns show fine agreement with each other at each frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.123-127
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• 2017

This paper fabricated and analyzed the image rejection mixer that uses FET's channel resistance. It can be applied for capacity 64QAM that has 50MHz~90MHz of IF band, 8.17GHz of LO frequency and 8.08~8.12GHz of RF band. When IF input power is -20dBm and LO input power is 10dBm, RF output power is obtained -33.2dBm. In this case, conversion loss is 12.9dB, the suppression of 14.3dB for LO frequency and 10.4dB for image frequency. The result of two tone test shows great IMD characteristics with 51.7dBc.