• Applied Microscopy
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• v.34 no.3
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• pp.159-170
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• 2004

Spermiogenesis in the Korean squirrel, Tamias sibiricus, was investigated by transmission electron microscopy. Spermiogenesis was divided into Golgi, cap, acrosome, maturation and spermiation phases based on the characteristics of acrosomal changes and nuclear shape. Beside, the Golgi, cap and acrosomal steps were subdivided into three phases of early, middle and late phase respectively, the maturation step was divided into two phases of early and late phase, and spermiation step has only one phase. Thus, the spermiognesis of T. sibiricus was divided into a total of twelve phases. In Golgi phase (steps 1-3), a well developed Golgi complex was located close to the vesicles, the acrosomal vesicle fixd to a recess of nuclear membrane at step 3. During cap phase (steps 4-6), the acrosomal vesicle spred over the nuclear surface to cover a third of the nucleus, and the acrosomal granule was not yet flattened. At acrosomal phase (steps 7-9), the nucleus and acrosome were elongated but nucleoplasm was not condensed. During maturation phase (steps 10-11), the nucleoplasm was more condensed, and the mitochondria completely arranged the center of axoneme. The spatulate-sperm head was completely formed at spermiation phase (step 12).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.239-244
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• 2004

In this paper, we have developed a frequency mixer which can be used as a microwave phase conjugator in the LS band retrodirective antenna system. The mixer as a phase conjugator must have an If signal of which frequency is nearly as high as that of an RF signal, so this fact brings difficulty in the combination of input signals and the design of impedance matching circuit. The circuit configuration is chosen to be of the gate mixer using a pseudomorphic HEMT device. The operating frequencies are 4.00 ㎓, 2.01 ㎓, and 1.99 ㎓ for LO, RF, and IF, respectively. Conversion gain is measured to be 12.5 ㏈ and 1 ㏈ compression point -34 ㏈m at the LO power of -7 ㏈m. The mixer fabricated in this research is the single-ended type, where RF leakage signal appears inevitably at the If port because RF and If frequencies are almost the same. The circuit topology suggested here can be applied directly to the design of balanced-type mixers and phase conjugators.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.1
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• pp.1-8
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• 2019

Most of rotor resistance estimators utilizes Classical qd Model (CQDM) and Alternate qd Model (AQDM). The rotor resistance estimators based on both models were shown to provide an accurate rotor resistance estimate under conditions where flux is constant such as a field-oriented control (FOC) based induction motor drives. Under the conditions where flux is varying such as a Maximum torque per amp (MTPA) control, AQDM based rotor resistance estimator estimates actual rotor resistance accurately even in different operating points. However, CQDM based rotor resistance estimator has not been investigated and its performance is questionable under condition where flux level is varying. Thus, in this work, the performance of CQDM based rotor resistance estimator was investigated and made comparisons with AQDM based estimator under conditions where flux level is significantly varying such as in MTPA control based induction motor drives. Unlike AQDM based estimator, the laboratory results show that the CQDM based estimator underestimates actual rotor resistance and exhibits an undesirable dip in the estimates in different operating points.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.4
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• pp.571-578
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• 2023

In this paper, we propose a low EMI data transmitter employing a delay-locked loop for vehicles. For the low EMI characteristic, the transmitter has been designed to have low slew rate and employs the delay-locked loop to correct the amount of change in the slew rate due to process variations. According to simulation results, the proposed transmitter which the delay-locked loop has smaller slew rate change as compared to the conventional transmitter. The proposed circuit has been designed with a 65nm process technology and the data rate is 20Mbps with a supply voltage of 1.1V. As compared to a conventional transmitter, the proposed transmitter shows that variations of the slew rate become 53.6% lower in a fast condition and 13.07% lower in a slow condition.

• Journal of the Korean Institute of Gas
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• v.28 no.1
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• pp.59-64
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• 2024

In this study, we conducted research on a miniaturized transmission system suitable for ultra-compact electric vehicles, such as electric arts or small electric cars. While conventional electric vehicles eliminate multi-gear transmissions and control motor output or secure initial driving force through reducers, in vehicles like electric karts or compact electric cars, which have relatively small battery capacities, the driving range can be reduced or the motor can be stressed epending on the loading state. Therefore, in this study, we developed a low stage ratio 0.625 and high stage ratio 1.6 a two-stage transmission system that can change gears as needed, considering factors such as slope conditions and loading status, by applying the continuously variable transmission (CVT) mechanism. Based on the selected gear ratios, we designed the transmission and created a test rig to verify the power transmission efficiency of the developed transmission. Using the test rig, we varied the rotational speed and load of the transmission to confirm its power transmission characteristics and also examined the heat generation characteristics during shifting and operation. As a result, developed a two-stage transmission with a CVT structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of Yeungnam Medical Science
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• v.15 no.2
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• pp.275-285
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• 1998

Sarcoma of the uterus is very rare malignant tumor originating from uterine muscle or connective tissue. We have experienced 20 cases of uterine sarcoma from January 1991 to June 1998. The results were as follows: 1. The pathologic types were 13 cases(65.0%) of leiomyosarcoma, 5 cases(25.0%) of malignant mixed Mullerian tumor, 1 case of rhabdomyosarcoma, and 1 case of angiosarcoma. 2. The average age and parity was 50.2 and 3.7. The chief complaints were irregular vaginal bleeding(35.0%), lower abdominal pain(25.0%), and abdominal mass(25.0%). 3. Nine cases(45.0%) were FIGO stage I, 1 case(5.0%) was stage II, 6 cases(30.0%) were stage III, and 4 cases(20.0%) were stage IV. 4. The survival was from 1.5 months to over 130 months(median 16.5 months), and there was no correlation between survival and FIGO stage or pathologic type. The correlation between survival and number of mitotic figure was incalcurable. 5. CA 125 levels were serially measured as a tumor marker in monitoring patients and the positive rate was 40%. Further study was needed to make a conclusion for usefulness of CA 125 as a tumor marker.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.40-48
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• 1998

Linear size expanders have been studied in many fields for the practical use, which make it possible to connect large numbers of device chips in both parallel communication systems and parallel computers. One major limitation on the efficiency of parallel computer designs has been the highly cost of parallel communication between processors and memories. Linear order concentrators can be used to construct theoretically optimal interconnection network schemes. Existing explicitly defined constructions are based on expanders, which have large constant factors, thereby rendering them impractical for reasonable sized networks. For these objectives, we use the more detailed matching points in permutation functions, to find out the bigger expansion constant from an equation, $\mid\Gamma_x\mid\geq[1+d(1-\midX\mid/n)]\midX\mid$. This paper presents an improvement of expansion constant on constructing concentrators using expanders, which realizes the reduction of the size in a superconcentrator by a constant factor. As a result, this paper shows an explicit construction of (n, 5, $1-\sqrt{3/2}$) expander. Thus, superconcentrators with 209n edges can be obtained by applying to the expanders of Gabber and Galil's construction.