• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.88-98
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• 2012

In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18 ${\mu}m$ CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33 ${\mu}W$, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW - power efficiency.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.18-20
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• 1997

The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.349-355
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• 2015

A fully-differential touch-screen sensing architecture is presented to improve noise immunity and also support most multi-touch events minimizing the number of amplifiers and their silicon area. A correlated double sampling function is incorporated to reduce DC offset and low-frequency noises, and a stabilizer circuit is also embedded to minimize inherent transient fluctuations. A prototype of the proposed readout circuit was fabricated in a $0.18{\mu}m$ CMOS process and its differential operation in response to various touch events was experimentally verified. With a 3.3 V supply, the current dissipation was 3.4 mA at normal operation and $140{\mu}A$ in standby mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

• 전기전자학회논문지
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• 제15권2호
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.629-633
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• 2015

An active balun using current steering for phase correction is presented. The proposed active balun is constructed with two different unit balun structures based on current steering to reduce phase and amplitude errors. This type of topology can be compared with the conventional phase and amplitude correction techniques which do not incorporate the current steering. Designed and fabricated active balun in $0.18{\mu}m$ CMOS process operates over 0.95 - 1.45 GHz band, showing input reflection coefficient under -15 dB, phase error of $11^{\circ}$ and gain error of 0.5 dB. Gain is measured to be 0.3 dB maximum and power consumption of 7.2 mW is measured.

• 전자공학회논문지CI
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• 제45권1호
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• pp.1-10
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• 2008

본 논문에서는 기존에 얼굴 검출에 사용된 ICT(Improved Census Transform) 변환을 이용하여 눈, 코, 입 등의 얼굴 특징을 검출하는 하드웨어를 설계하였다. 파이프라인 구조를 이용하여 동작 속도를 높였고, ICT 변환, 메모리 공유, 동작 과정의 세분화를 통하여 메모리 사용량을 줄였다. 본 논문에서 사용한 알고리즘을 얼굴 검출 및 인식 분야에서 테스트용으로 주로 쓰이는 BioID 데이터베이스(database)를 이용하여 테스트한 결과 100%의 검출률을 보였고, 설계한 하드웨어의 결과도 이와 동일하였다. 또한 Synopsys사의 Design Compiler와 동부아남사의 $0.18{\mu}m$ library를 이용하여 합성한 결과 총 $376,821{\mu}m2$의 결과를 얻었고 78MHz의 동작 클럭 하에서 17.1msec의 검출 속도를 보였다. 본 논문은 소프트웨어 형태의 알고리즘을 임베디드 하드웨어로 구현함으로 인하여 실시간 처리의 가능성을 보였고, 저가격, 높은 이식성에 대한 가능성을 제시하였다.

• 대한전자공학회논문지SD
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• 제44권9호
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• pp.34-39
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• 2007

백플레인 채널 시리얼 링크는 심각한 신호왜곡 현상을 겪는다. 특히, 채널 자체의 특성에 의해 발생하는 이득손실, 주파수에 따른 손실, 반사파 등의 불완전성으로 더욱 심해진다. 이 중 주파수에 따른 손실의 경우 신호파형에 ISI를 일으키므로, 이를 줄이기 위해 어댑티브 이퀄라이저 회로를 사용한다. 본 논문에서는 0.18um CMOS공정을 이용하여 구현한 아날로그 형태의 10Gb/s 어댑티브 이퀄라이저 회로를 소개한다. 제안한 이퀄라이저 회로는 34인치의 긴 백플레인 채널(혹은 트랜스미션 라인)의 불완전성에도 불구하고, 매우 높은 동작속도(10Gb/s)를 유지한다. 포스트 레이아웃 시뮬레이션 결과, 제안한 회로는 10mW의 전력소모와 $8ps_{p-p}$의 지터 특성을 가지며, $0.56mm^2$의 칩 사이즈를 갖는다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.441-442
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• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band $(860{\sim}960MHz)$ and is also applicable to mobile RFID readers. It is designed using a $0.18{\mu}$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100kHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$