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A 10Gb/s Analog Adaptive Equalizer for Backplanes  

Yoo, Kwi-Sung (Department of Electrical and Electronic Eng., Yonsei University)
Han, Gun-Hee (Department of Electrical and Electronic Eng., Yonsei University)
Park, Sung-Min (Department of Information Electronics Eng., Ewha Womans University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.9, 2007 , pp. 34-39 More about this Journal
Abstract
Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.
Keywords
adaptive equalizer; backplane channel; ISI; pre-emphasis filter; serial links;
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