• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.445-453
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• 2015

A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a $0.18-{\mu}m$ CMOS process occupies an area of $750{\mu}m{\times}610{\mu}m$. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes $3{\mu}A$ under normal operating conditions and $0.45{\mu}A$ under standby mode.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.798-805
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• 2015

This paper proposes Relaxation Oscillator with Random Number Generator to minimize electromagnetic interference (EMI) noise. DC-DC Converter with Relaxation Oscillator is presented how much spurious noise effects to RF Receiver system. The main frequency of the proposed Relaxation oscillator is 7.9 MHz to operate it and add temperature compensation block to be applied to the frequency compensation in response to temperature changes. The DC-DC Converter Spurious noise is reduced up to 20 dB through changing frequency randomly. It is fabricated in $0.18{\mu}m$ CMOS technology. The active area occupies an area of $220{\mu}m{\times}280{\mu}m$. The supply voltage is 1.8 V and current consumption is $500{\mu}A$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.98-101
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• 2007

A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• Journal of IKEEE
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• v.19 no.4
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• pp.573-582
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• 2015

This paper presents the design of dual mode boost converter for energy harvesting. The designed converter boosts low voltage from energy harvester through a startup circuit. When the voltage goes above predefined value, supplied voltage to startup circuit is blocked by voltage detector. Boost controller makes the boosted voltage into $V_{OUT}$. The proposed circuit consists of oscillator for charge pump, charge pump, pulse generator, voltage detector, and boost controller. The proposed converter is designed and fabricated using a $0.18{\mu}m$ CMOS process. The designed circuit shows that minimum input voltage is 600mV, output is 3V and startup time is 20ms. The boost converter achieves 47% efficiency at a load current of 3mA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.869-872
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• 2005

This paper presents a new switchable dual mode VCO(Voltage-Controlled Oscillator). The VCO is efficient in dual mode operation and has self-bias adjustment based on the operation frequencies of 2.4 GHz and 5 GHz. The switching is done using MOS transistors and tuning is done using MOS varactors. It is implemented using TSMC 0.18${\mu}$m CMOS technology. It is powered by 1.8V supply. The measured results showed that the overall tuning range is approximately 13% at 5 GHz and 8% at 2.4 GHz. The measured phase noise is approximately -102 dBc/Hz at 1 MHz offset for 5 GHz and -89 dBc/Hz at 600kHz offset for 2.4 GHz. The VCO showed tail currents of 2mA in 5GHz mode and 2.5mA in 2.4GHz mode from a 1.8 V supply, respectively.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.342-347
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• 2017

We present a precision instrument amplifier (IA) designed for bio-potential acquisition. The proposed IA employs a capacitively coupled instrument amplifier (CCIA) structure to achieve a rail-to-rail input common-mode range and low gain error. A positive feedback loop is applied to boost the input impedance. Also, DC servo loop (DSL) with pseudo resistors is adopted to suppress electrode offset for bio-potential sensing. The proposed amplifier was designed in a $0.18{\mu}m$ CMOS technology with 1.8V supply voltage. Simulation results show the integrated noise of $1.276{\mu}Vrms$ in a frequency range from 0.01 Hz to 1 KHz, 65dB SNR, 118dB CMRR, and $58M{\Omega}$ input impedance respectively. The total current of IA is $38{\mu}A$. It occupies $740{\mu}m$ by $1300{\mu}m$ including the passive on-chip low pass filter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.