• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.31-32
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• 2015

본 논문은 FAC (Forward converter Active Clamp) 회로를 통해 변압기 자화인덕턴스에 저장된 에너지를 셀 밸런싱에 재사용하는 Active Clamp Forward converter 기반 셀 밸런싱 회로를 제안한다. 제안 회로는 클램프 커패시터의 충전 균형으로 스위치를 전압 스파이크로부터 보호하고 전력손실을 초래할 수 있는 변압기의 자기포화를 방지할 수 있다. 제안한 셀 밸런싱 회로는 RCD 포워드 셀 밸런싱 컨버터 보다 더 높은 전력 전달 효율과 낮은 전압 스트레스를 갖는다. 제안한 액티브 셀 밸런싱 회로는 동시에 모든 셀이 균등화 되도록 작동하므로, 셀밸런싱 시간이 짧다. 본 논문에서는 제안 회로의 배터리 상태에 따른 제어모드를 설명하고 회로의 타당성 검증을 위해 Powersim 사(社)의 Psim 시뮬레이션 연구를 수행하였다.

• 전기의세계
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• v.29 no.6
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• pp.354-361
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• 1980

Weil-Dobke 회로 및 2-parameter TRV회로의 문제점을 검토하고 비교적 간단한 네가지의 4-parameter TRV 회로에 대한 기초적인 검토가 이루어졌으나 현단계에서 각 회로에 대한 회로계산등의 적극적인 검토를 할 수는 없었고 앞으로 컴퓨터나 TNA등의 설비를 이용할 수 있을 경우 전반적인 비교검토를 하고 그것을 바탕으로 우리 연구소의 기존 설비를 최대로 활용할 수 있는 회로를 채택하는 것이 바람직하다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.249-254
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• 2011

This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.652-654
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• 2016

This paper shows the Design and implementation of sinusoidal BLDC motor drive logic using SVPWM method with FPGA. Sinusoidal BLDC motor driver logic consists of sine-wave PWM generator, dead-time and lead angle control logic. PWM generator logic is designed using SVPWM method for increase of 15.5% linear domain than general sine-wave PWM. This logic is verified and implemented using Spartan-6 FPGA Board. Test results show that THD(Total Harmonic Distortion) of motor-driving current is 19.2% and rotor position resolution is 1.6 degree.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• Journal of The Korean Society of Grassland and Forage Science
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• v.5 no.1
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• pp.84-89
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• 1985

Chemical composition, dry matter and cellulose digestibilities and fermentation rates of alfalfa and orchard grass cut at different time were estimated in vitro method and the results summurized as follows: 1. Crude protein, crude fiber cwc and cellulose content of Alfalfa were decreassed as advancing cutting time. Crude protein, crude fiber and cwc content of Orchard grass were decreased as advancing cutting time up to 3 cutting, but crude protein was slightly increased at 4th cutting, crude fiber and cellulose content were higher at 2nd cutting, but decreased thereafter. 2. DM digestibility of Alfalfa was 51.80, 51.86, 52.92 and 59.52% at 1, 2, 3 and 4th cutting time, respectibly, thus slightly increased as advancing cutting time, and cellulose digestibility of Alfalfa was not much different with different cutting time. DM digestibility of Orchard grass was 62.21, 66.10, 60.95 and 66.32% at 1, 2, 3 and 4th cutting time, respectibly, and cellulose digestibility of Orchard grass was slightly increased at 3rd cutting time and then increased at 4th cutting time. 3. Fermentation rate of DM of alfalfa was the highest 1st cutting time (0.83%/hr.) and was not different at 3 and 4th cutting time. Cellulose fermentation rate of Alfalfa was the highest at 1st cutting time (1.29%/hr.), decreased at 2 and 3th and then increased at 4th cutting time. Fermentation rate of DM of Orchard grass was 1.42, 1.58, 1.60 and 1.57%/hr. and of cellulose was the highest at 2nd cutting time (1.77%/hr.)

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.60-61
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• 2016

본 논문에서는 interleaved 벅-컨버터를 영-전압 스위칭으로 구동하기 위한 새로운 회로를 제안한다. 제안하는 회로는 두개의 벅-컨버터 모듈과 보조 회로로 구성된다. 보조 회로는 coupled-inductor와 커패시터로 구성된다. Coupled-inductor에 흐르는 전류가 스위치가 꺼지기 전에 스위치의 전류의 방향을 바꾸어서 영 전압 스위칭을 달성한다. 제안하는 회로는 보조회로에 반도체 소자를 추가하지 않고 수동 소자만으로 구성하여 신뢰성의 저하를 막는다. 또한 수동 소자만으로 구성된 보조 회로로 인해 발생하는 도통 손실의 증가를 최소화 한다. 제안하는 회로는 시뮬레이션을 통해 검증하였다.