• Title/Summary/Keyword: 회로저항

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Middle and High School Students' Mental Representation on Electric Circuits (중.고등학교 학생들의 전기 회로도에 관한 표상)

  • Choi, Kwan-Soon;Park, Yang-Yoon;Kim, Beom-Ki
    • Journal of The Korean Association For Science Education
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    • v.24 no.3
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    • pp.612-620
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    • 2004
  • The purpose of this study was to investigate how middle and high school students represent circuit diagrams with different shapes but electrically same. What prototypes of circuit which students possessed were, how students represented the connection of resistors, and what criteria used while grouping the circuit diagrams were investigated. The participants were 10 middle and 10 high school students. The results show that they represented the circuit diagrams by the geometrical resistor configurations rather than physics principles, not considering the presence of a junction or a battery on the branch. This representation was constrained by the circuit prototypes. Middle and High school students seems to have the own way of representing circuit diagrams without considering physics principles.

A Study on composition of current stable negative resistance circuits. (전류안정부저항회로의 구성에 관한 연구)

  • 박의열
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.10 no.1
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    • pp.9-17
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    • 1973
  • This paper dealt with composition of current stable negatil'e resistance circuit based on Beam resistance of the tube SAMUEL SEBLY suggested. Beam resistance which is decreased by input current increment on definite region of current, accompanied generation of equivalent e. m. f on model circuit. With equivalent e. m. f there appeared increased current on circuit but decrease of terminal voltage. Bloc constructed by above concept induced transistorized circuit which have NPN and a PNP Transistor. Circuit operation predicted and calculated values of negative resistance are coincident with experimental results. A Circuit proposed on this paper sllowed good linearity on Ve-Ji characteristics.

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Design of sense amplifier with self-bias circuit in CCID (전하 결합 영상소자에서 전압 분배 회로가 있는 감지회로의 설계)

  • Park, Yong;Kim, Yong-Kook;Lee, Young-Hee
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.511-513
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    • 1998
  • 본 연구는 영상소자의 감도를 향상 시키기 위하여 전압 분배 회로를 가진 감지 회로를 설계하였다. 전압분배 회로는 NMOSFET과 Poly 저항의 두 경우로 설계하였으며 감지 회로에 흐르는 전류는 전압 분배 회로를 NMOSFET으로 설게하였을때가 Poly 저항으로 구성한 경우보다 적게 흐르며 감도 특성도 좋은 것으로 나타났다. 또한 poly 저항보다 NMOSFET을 이용한 전압 분배 회로가 동작 주파수에 따른 특성이 우수하였다.

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A Study on composition of the negative resistance circuit (부저항특성회로의 구성에 관한 연구)

  • 박의열
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.10 no.6
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    • pp.11-24
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    • 1973
  • A new simple technique for 2-terminal negative resistance cireait analysis and synthesis is developed, by using the equivalent e.m.f. defined as a function of input lotage or current variation. The technique is applied to design 2-terminal junction transistor negative resistance circuits based on the parameter control method. Modeling circuits for SCR, GTO-SCR and SSS are also derived from the proposed transistor negative resistance circuits, and the merits of the modeling circuits are discussed.

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Buck Converter analysis and controller design considering parasitic resistance of inductor and capacitor (인덕터, 커패시터의 기생저항을 고려한 Buck Converter 해석 및 제어기 설계)

  • Lee, Kyu-Min;Kim, Il-Song
    • Proceedings of the KIPE Conference
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    • 2019.07a
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    • pp.487-488
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    • 2019
  • 본 연구는 인덕터, 커패시터의 기생저항을 고려한 Buck Converter의 회로 해석 및 Two Loop Control 방법의 제어기 설계를 제안한다. 일반적인 Buck Converter의 회로 및 제어기 설계에서는 인덕터, 커패시터의 기생저항의 값이 작아 0으로 간주한다. 본 논문에서는 인덕터와 커패시터의 기생저항을 고려한 회로를 수학적으로 해석한 뒤 Matlab SISOTOOL을 이용하여 전압 및 전류 제어기를 설계하고 PSIM을 통해 회로를 구성하여 시뮬레이션을 통해 검증함으로써 일반적인 설계보다 정확성을 가진 설계방법을 제안한다.

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Determination of divider resistance in voltage divider circuits used NTC thermistor. (NTC thermistor를 사용한 voltage divider 회로에서 divider resistance결정)

  • Ku, Ja-Hun;Kim, Jong-Dae;Kim, Yu-Seop;Park, Chan-Young;Lee, Wan-Yeon;Song, Hae-Jung
    • Proceedings of the Korean Information Science Society Conference
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    • 2010.06c
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    • pp.221-225
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    • 2010
  • 본 연구에서는 제한된 온도 영역에서 보통 정밀 온도 측정 소자로 많이 쓰이는 NTC 써미스터를 사용하여 전압 분배 회로(voltage divider circuits)를 구성하였다. 분압 저항이 온도측정 해상도에 미치는 영향을 분석하고, 회로의 분압 저항을 결정하는 방법으로서 측정하고자 하는 온도 구간의 최대 온도와 최저 온도의 NTC 써미스터 저항 값을 조화평균을 사용하여 분압 저항(divider resistance)으로 사용하였다. 선택한 분압 저항이 이상적인 저항인지에 대하여 조화평균으로 계산한 분압 저항과 대조군 저항으로 전압 분배 회로를 병렬로 구성하였다. 센서들을 항온조 넣어 설정온도($50^{\circ}C$, $70^{\circ}C$, $90^{\circ}C$)에서 각각의 온도를 측정한 후 측정 데이터의 표준편차를 구하여 평균 온도 분해능을 비교 하는 실험을 하였다. 실험결과 측정온도 구간의 최대 온도와 최소 온도에서의 NTC 써미스터 저항 값을 조화평균으로 계산한 분압 저항 값이 대조군 저항에 비해 설정온도에서 보다 높은 평균 온도 분해능(sensing resolution)을 보였다.

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A Versatile Design of Optronic Negative Resistance (호용성이 있는 광결합 부성저항회로의 설계)

  • 박성한
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.15 no.4
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    • pp.33-37
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    • 1978
  • A versatile negative resistance using one transistor, one photo-coupler and three resisters, which can be used as either a voltage controlled or current controlled negative resistance, is designed. The versatility is obtained by changing the transistor and one connection of the circuit. The negative resistance region is linear and its value can be varied by varying one of the three resistor values.

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Non-Contact Sensing Method using PT Symmetric Circuit with Cross-Coupled NDR Circuits (크로스-결합구조의 부성 미분 저항 회로를 이용한 페리티-시간 대칭 구조의 비접촉 센서 구동 회로에 대한 연구)

  • Hong, Jong-Kyun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.22 no.4
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    • pp.10-16
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    • 2021
  • This paper proposes a model that considers the parity-time symmetric structure as a state detection circuit for sensor applications using a stretchable inductor. In particular, to obtain a more practical computer simulation result, the stretchable inductor model was applied to this study model by referring to previously reported experimental results. The resistance component and phase component were controlled through the negative differential resistance circuit used in this study. In addition, the imbalance of the circuit caused by a change in the characteristics of the stretchable inductor could be compensated for using a negative differential resistance circuit. In particular, an analysis of the frequency characteristics of the sensor driving circuit of the parity-time symmetric structure proposed in this study confirmed that the Q-factor could be increased up to 20 times compared to the conventional resonant circuit.

The Hardware Implementation of Chua's Oscillator (Chua 발진기 회로의 하드웨어 구현)

  • 배영철;강명구
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.3
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    • pp.553-561
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    • 2001
  • Chua's oscillator is a simple electronic circuit which exhibits a variety of bifurcation phenomena and attractors, It consist of two capacitors, an inductor, two linear resistors, and a nonlinear resistor. When the circuit exhibits chaotic signals, the nonlinear resistor of Chua's oscillator may have six different voltage - current characteristics. In this paper, the design methodology for practical implementation of the nonlinear resistors which have all these characteristics is described. In addition, the effectivness of result is shown by not only the computer simulation but also the experimental test.

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An Efficient Bias Circuit of Discrete BJT Component for Hearing Aid (보청기를 위한 개별 BJT 소자의 효과적인 바이어스 회로)

  • 성광수;장형식;현유진
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.16-23
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    • 2003
  • In this paper, we propose an efficient bias circuit of discrete BJT component for hearing aid. The collector feedback bias circuit, widely used for the hearing aid, has a resistor for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor to the collector feedback bias circuit between base and power supply which is $\beta$ times target than the collector resistor. Thus. we can change amplifier gain without changing DC bias point, and reduce power noise gain about 18.5% compare to that of tile previous circuit in the simulation.