• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.39-47
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• 2005

The range of hardware implementation increases in communication systems as high-speed processing is required for high data rate. In the broadband wireless access (BWA) system based on IEEE standard 802.16 the functions of higher part in the MAC layer to Provide data needed for generating MAC PDU are implemented in software, and the tasks from formatting MAC PDUs by using those data to transmitting the messages in a modem are implemented in hardware. In this paper, the interface hardware for efficient message exchange between MAC and PHY layers in the BWA system is designed. The hardware performs the following functions including those of the transmission convergence(TC) sublayer; (1) formatting TC PDU(Protocol data unit) from/to MAC PDU, (2) Reed-solomon(RS) encoding/decoding, and (3) resolving DL MAP and UL MAP, so that it controls transmission slot and uplink and downlink traffic according to the modulation scheme of burst profile. Also, it provides various control signal for PHY modem. In addition, the truncated binary exponential backoff (TBEB) algorithm is implemented in a subscriber station to avoid collision on contention-based transmission of messages. The VLSI architecture performing all these functions is implemented and verified in VHDL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1078-1091
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• 2011

In this paper, a triple band-notched UWB antennas using a spiral resonator and a complementary split ring resonator is proposed as two types. The band-rejection characteristic of the designed antenna is analyzed through the structure and equivalent circuit model of spiral resonator and CSRR. The measured results of first type antenna show that a VSWR less than 2 was satisfied with a resonant frequency in the range of 1.16~12 GHz and it can be obtained the band-stop performance at 3.3~3.85 GHz, 5.15~6.1 GHz, and 8.025~8.5 GHz. The measured results of second type antenna show that a VSWR less than 2 was satisfied with this antenna works from 1.79 to 12 GHz and it can be achieved the band-notched performance at 3.3~3.88 GHz, 5.12~5.94 GHz, and 8.025~8.51 GHz. Through the measured results, the designed antenna was satisfied UWB band except for triple notched bands.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.31-38
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• 2011

A RAM-based Neural Net is a weightless neural network based on binary neural network. 3-D neural network using this paper is binary neural network with multiful information bits and store counts of training. Recognition method by MRD technique is based on the supervised learning. Therefore neural network by itself can not distinguish between the categories and well-separated categories of training data can achieve only through the performance. In this paper, unsupervised learning algorithm is proposed which is trained existing 3-D neural network without distinction of data, to distinguish between categories depending on the only input training patterns. The training data for proposed unsupervised learning provided by the NIST handwritten digits of MNIST which is consist of 0 to 9 multi-pattern, a randomly materials are used as training patterns. Through experiments, neural network is to determine the number of discriminator which each have an idea of the handwritten digits that can be interpreted.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.293-299
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• 2003

In this paper, we have proposed a high conversion and isolation characteristic V-band quadruple sub-harmonic mixer monolithic circuit which is designed and fabricated for the millimeter wave down converter applications. While most of the sub-harmonic mixers use a half of fundamental frequency, we adopt a quarter of the fundamental frequency. The proposed circuit is based on a sub-harmonic mixer with APDP(anti-parallel diode pair) and the 0.1 ${\mu}{\textrm}{m}$ PHEMT's (pseudomorphic high electron mobility transistors). Lumped elements at IF port provide better selectivity of IF frequency and increase isolation. Maximum conversion gain of 0.8 ㏈ at a LO frequency of 14.5㎓ and at a RF frequency of 60.4 ㎓ is measured. Both LO-to-RF and LO-to-IF isolations are higher than 50 ㏈. The conversion gain and isolation characteristic are the best performances among the reported quadruple sub-harmonic mixer operating in the V-band millimeter wave frequency thus far.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.1
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• pp.27-34
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• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.