• Journal of the Korean Crystal Growth and Crystal Technology
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• v.31 no.6
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• pp.276-281
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• 2021

In order to manufacture a semiconductor circuit, etching, cleaning, and deposition processes are repeated. During these processes, the inside of the processing chamber is exposed to corrosive plasma. Therefore, the coating of the inner wall of the semiconductor equipment with a plasma-resistant material has been attempted to minimize the etching of the coating and particle contaminant generation. In this study, we synthesized yttrium oxyfluoride (YOF) powder by a solid-state reaction using Y₂O₃ and YF₃ as raw materials. Mixing ratio of the Y₂O₃ and YF₃ was varied from 1.0:1.0 to 1.0:1.6. Effects of the mixing ratio on crystal structure and microstructure of the synthesized YOF powder were investigated using XRD and FE-SEM. The synthesized YOF powder was successfully applied to plasma spray coating process on Al substrate.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.28 no.3
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• pp.171-174
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• 2022

Cosmetic packing materials tend to be difficult to recycle when discarded due to the cosmetic industry's pursuit of aesthetics, functionality, and high value-added design. Pump packaging, which is widely used for the good preservation and discharge of cosmetics contents, is difficult to be separated and recycled because of a metal spring, which is in charge of pump resilience. In this study, a polypropylene spring was developed to replace the existing metal spring to improve the recyclability of the pump packaging for cosmetics, and was uni-materialized by applying to the cosmetic packing materials with 0.2 ml of discharge amount. In addition, performance test was conducted to verify the equivalence with the existing metal spring pumps as grounds for the commercialization of metal-free uni material pump packaging. The decompression leak test showed no leakage and displayed 14.8~17.5 N of pressing strength, 2.3~8.8 % of deviation in dispensing volume, and 4 occasions of pumping for initial discharge.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.33 no.4
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• pp.153-157
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• 2023

In order to manufacture a semiconductor circuit, etching, cleaning, and deposition processes are repeated. During these processes, the inside of the processing chamber is exposed to corrosive plasma. Therefore, the coating of the inner wall of the semiconductor equipment with a plasma-resistant material has been attempted to minimize the etching of the coating and particle contaminant generation. In this study, we mixed AlF₃ powder with the solid-state reacted yttrium oxyfluoride (YOF) in order to increase plasma-etching resistance of the plasma spray coated YOF layer. Effects of the mixing ratio of AlF₃ with YOF powder on crystal structure, microstructure and chemical composition were investigated using XRD and FE-SEM. The plasma-etching ratios of the plasma-spray coated layers were calculated and correlation with AlF₃ mixing ratio was analyzed.

• Journal of the Korea institute for structural maintenance and inspection
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• v.28 no.2
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• pp.27-34
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• 2024

This study was conducted to examine the feasibility of using Fe-activated wood-derived biochar as a conductive filler for manufacturing cement-based strain sensor. To evaluate the compressive and electrical properties of cement composite with 3% Fe-activated biochar, three cubic specimens of size 50 x 50 x 50mm³ and three prismatic cement-based sensors of size 40 x 40 x 80mm³ were prepared respectively. The four-probe method of electrical resistance measurement was used for cement-based sensors. For cement-based sensors with FE-activated biochar, the conductive performance such as electrical resistance and impedance under different water content and repeated compression was investigated. Results showed that the fractional changes in the DC electrical resistivity of cement-based sensors increase with increasing time and the maximum fractional changes in the resistivity decrease with increasing the moisture contents during 900s. At moisture content of 7.5% range, the conductive performance of cement composite including 3% Fe-activated biochar as a conductive filler showed the most stable, while the strain detection ability tended to decrease somewhat as the repeated compressive stress increased between repeated compressive strain and fractional change in resistivity (FCR).

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Korean Geographical Society
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• v.31 no.4
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• pp.685-698
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• 1996

Southern Louisiana has one of the largest Vitnamese refrgee neighborhoods after the mid-1970s. It is impressive that one of their adaptive strategies comes from their religious lives which are centered on either Catholicism or Buddhism. The Buddhism community, especially, exhibits an exotic symbolic system of value and attitude, and thus contributes to cultural diversity in the adopted country. The landscape of the Buddhist temple is a visible symbol to them that the host socirty accepts their maintenance of their own cultural identity and that they are also an integral part of American society. Their making-place and being-in-place procedures, although their culture is being transformed in the original shape, put an emphasis on interaction with the host xociety. These procedures have been facilitated by consolidating their identity as a minority group as well as by interacting with the host society. The on-going influx of foreign immigrant groups seems not to drive them to assimilate into the melting-pot society, but to contribute to contribute to the increase in the cultural diversity of the United States.

• The korean journal of orthodontics
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• v.33 no.3 s.98
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• pp.185-197
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• 2003

This study was performed to identify the characteristics of the OFC1 gene (locus: chromosome 6p24.3) in Korean patients, which is assumed to be the major gene behind the nonsyndromic cleft lip and palate. The sample consisted of 80 subjects: 40 nonsyndromic cleft lip and palate patients (proband, 20 males and females, mean age 14.2 years); and 40 normal adults (20 males and 20 females, mean age 25.6 years). Using PCR-based assay, the OFC1 gene was amplified, sequenced, and then searched for similar protein structures. Results were as follows: 1. The OFC1 gene contains the microsatellite marker 'CA' repeats. The number of the reference 'CA' repeats was 21 times, and formed as TA(CA)11TA(CA)10. But, in Koreans, the number of tandem 'CA' repeats was varied from 17 to 26 except 18, and 'CA' repeats consisted of TA(CA)n. 2. Nine allelic variants were found. Distribution of the OFC1 allele was similar between the patients and control group. 3. There was a replacement of the base 'T' to 'C' after 11 tandem 'CA' repeats in Koreans compared with Weissenbach's report. However, the difference did not seem to be the ORF prediction results between Koreans and Weissenbach's report. 4. The BLAST search results showed the Telomerase reverse transcriptase (TERT) and the Nucleotide binding protein 2 (NBP2) as similar proteins. The TERT was a protein product by the hTERT gene in the locus 5p15.33 (NCBI Genome Annotation; NT023089) The NBP2 was a protein product by the ABCC3 (ATP-binding cassette, sub-family C) gene in the locus 17q22 (NCBI Genome Annotation; NT010783). 5. In the Pedant-Pro database analysis, the predictable protein structure of the OFC1 gene had at least one transmembrane region and one non-globular region.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.47-54
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• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.