• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.696-698
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1741-1746
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.842-846
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• 2015

In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the digital circuit.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1076-1081
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• 2007

In this paper, we propose a new switch structure for time division duplex(TDD) system. The existing TDD structure utilizes a circulator fur isolation characteristic between ports. However, the circulator produces intermodulation distortion signals which are undesired signal because of its nonlinear properties. The proposed circuit is composed of a modified branch-line hybrid coupler which controls the signal flow while the isolated port is open-/short- terminated. In order to prove the validity of the presented structure, the switch circuit is fabricated and measured at 2.3GHz, the center frequency of Wibro service system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2745-2750
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• 2015

Abstract should be placed here In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the dital circuit.

• Review of KIISC
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• v.14 no.2
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• pp.78-88
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• 2004

정보 통신과 반도체 공정 기술의 급격한 발전으로 나노기술이 가까운 시일 내에 실용화되고, 유비쿼터스 환경이 도래할 것으로 예측된다. 나노기술 환경에서 사용되는 디바이스의 고집적도, 낮은 구동 능력, 배선 제약 특성이 정보 보호 분야에 사용되는 프로세서 구조와 회로 설계 기술을 크게 바꿀 것으로 예측된다. 본 연구에서는 이러한 기술 변혁에 대비하기 위해 나노기술 환경에 적합한 차세대 정보 보호 프로세서 구조와 회로 설계 기술을 분석하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.27-32
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• 2002

본 논문에서는 NOP 이 차지하는 슬롯에 의미 있는 명령어를 중복 할당하여 자료의존 관계를 해소하고 프로그램 실행 사이클을 단축시키는 명령어 중복 스케줄링 기법을 적용할 수 있는 VLIW 구조인 TiPs(Tiny Processors) 구조를 제안하였으며 TiPs는 회로의 복잡도를 증가시키지 않으면서 실행시간을 단축시켜 가상의 바이패싱 회로를 추가한 효과를 얻을 수 있다. 실험 결과 TiPs에서 명령어 중복 스케줄링 기법을 적용할 경우 8% ～ 25%의 성능 향상 효과가 있음을 알 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.85-87
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• 2010

본 논문에서는 공통 결함접지구조를 이용하여 브랜치 라인 하이브리드 커플러 회로를 소형화하여 설계한 결과를 제시한다. 브랜치 라인 하이브리드 커플러 회로는 가장 널리 쓰이는 전자파회로중 하나이다. 본 논문에서 제안하는 공통 결함접지구조를 이용하여 소형화한 커플러 회로는 크기가 소형화되었음에도 불구하고, 기존 커플러 구조와 유사한 정합, 격리 및 전력분배 특성을 보여준다.